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67 Commits

Author SHA1 Message Date
Aleksandar Beserminji a330c208f2 [mips] Include EVA instructions in Std2MicroMips mapping tables 
This patch includes EVA instructions in the Std2MicroMips mapping
tables, which is required for direct object emission.

Differential Revision: https://reviews.llvm.org/D41771

llvm-svn: 323958
 2018-02-01 12:53:26 +00:00
Simon Dardis 0d378a9eed [mips][micromips] Fix (dis)assembly of bc1(t|f) 
Previously these instructions were marked codegen only and had
an under-specified instruction description that did not record the
fcc register.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D38847

llvm-svn: 315905
 2017-10-16 14:20:22 +00:00
Simon Dardis 730fdb73a1 [mips] Correct c.cond.fmt instruction definition. 
Permit explicit $fcc<X> operand in c.cond.fmt instruction.

Add c.cond.fmt to the MIPS to microMIPS instruction mapping table.

Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for
c.cond.fmt, bc1t, bc1f.

Reviewers: seanbruno, zoran.jovanovic, vkalintiris

Differential Revision: https://reviews.llvm.org/D24510

llvm-svn: 292117
 2017-01-16 13:55:58 +00:00
Simon Dardis 9c34854833 [mips] synci microMIPS instruction definition. 
Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci
as not being part of microMIPS. This does not cover the sync instruction alias,
as that will be handled with a different patch. Add sync to the valid tests for
microMIPS.

Reviewers: vkalintiris

Differential Revision: https://reviews.llvm.org/D25795

llvm-svn: 284962
 2016-10-24 10:23:59 +00:00
Simon Dardis ba92b034bf Revert "[mips] Fix c.<cc>.<fmt> instruction definition." 
This reverts commit r281022. Mips buildbot broke, due to unhandled register
class FCC.

llvm-svn: 281033
 2016-09-09 11:06:01 +00:00
Simon Dardis 8efa979029 [mips] Fix c.<cc>.<fmt> instruction definition. 
As part of this effort, remove MipsFCmp nodes and use tablegen
patterns rather than custom lowering through C++.

Unexpectedly, this improves codesize for microMIPS as previous floating
point setcc expansions would materialize 0 and 1 into GPRs before using
the relevant mov[tf].[sd] instruction. Now $zero is used directly.

Reviewers: dsanders, vkalintiris, zoran.jovanovic

Differential Review: https://reviews.llvm.org/D23118

llvm-svn: 281022
 2016-09-09 09:22:52 +00:00
Hrvoje Varga 846bdb746d [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions 
Differential Revision: https://reviews.llvm.org/D22347

llvm-svn: 277719
 2016-08-04 11:22:52 +00:00
Hrvoje Varga 24b975dc66 [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions 
Differential Revision: http://reviews.llvm.org/D16625

llvm-svn: 273850
 2016-06-27 08:23:28 +00:00
Zlatko Buljan 6afea51a58 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D15418

llvm-svn: 269883
 2016-05-18 06:54:59 +00:00
Hrvoje Varga c2dd5d223a [mips][microMIPS] Revert commit r267137 
Commit r267137 was the reason for failing tests in LLVM test suite.

llvm-svn: 267419
 2016-04-25 15:40:08 +00:00
Hrvoje Varga 5560998250 [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions 
Differential Revision: http://reviews.llvm.org/D19354

llvm-svn: 267137
 2016-04-22 11:18:40 +00:00
Zlatko Buljan 797c2aec6b [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions 
Differential Revision: http://reviews.llvm.org/D11406

llvm-svn: 252885
 2015-11-12 13:21:33 +00:00
Hrvoje Varga 3ef4dd7bc8 [mips][microMIPS] Implement LLE and SCE instructions 
Differential Revision: http://reviews.llvm.org/D11630

llvm-svn: 250379
 2015-10-15 08:11:50 +00:00
Hrvoje Varga a766eff5a0 [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions 
Differential Revision: http://reviews.llvm.org/D11631

llvm-svn: 250377
 2015-10-15 07:23:06 +00:00
Zoran Jovanovic 6e6a2c9cd7 [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions 
Differential Revision: http://reviews.llvm.org/D9189

llvm-svn: 247780
 2015-09-16 09:14:35 +00:00
Zoran Jovanovic d9790793d6 [mips][microMIPS] Implement CACHEE and PREFE instructions 
Differential Revision: http://reviews.llvm.org/D11628

llvm-svn: 247125
 2015-09-09 09:10:46 +00:00
Zoran Jovanovic 416886793f [mips][microMIPS] Implement movep instruction 
Differential Revision: http://reviews.llvm.org/D7465

llvm-svn: 228703
 2015-02-10 16:36:20 +00:00
Jozef Kolek e10a02ecf0 [mips][microMIPS] Implement LWGP instruction 
Differential Revision: http://reviews.llvm.org/D6650

llvm-svn: 227325
 2015-01-28 17:27:26 +00:00
Jozef Kolek 5cfebdde2b [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B 
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226657
 2015-01-21 12:39:30 +00:00
Jozef Kolek 2c6d73207e [mips][microMIPS] Implement ADDIUPC instruction 
Differential Revision: http://reviews.llvm.org/D6582

llvm-svn: 226656
 2015-01-21 12:10:11 +00:00
Jozef Kolek 0d49117769 Reverted revision 226577. 
llvm-svn: 226595
 2015-01-20 19:29:28 +00:00
Jozef Kolek 45f7f9c1ab [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B 
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226577
 2015-01-20 16:45:27 +00:00
Jozef Kolek 9761e96b01 [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions 
Differential Revision: http://reviews.llvm.org/D5271

llvm-svn: 225627
 2015-01-12 12:03:34 +00:00
Jozef Kolek ab6d1cce3e [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions 
Differential Revision: http://reviews.llvm.org/D5204

llvm-svn: 224785
 2014-12-23 19:55:34 +00:00
Jozef Kolek 12c6982b3b [mips][microMIPS] Implement LWSP and SWSP instructions 
Differential Revision: http://reviews.llvm.org/D6416

llvm-svn: 224771
 2014-12-23 16:16:33 +00:00
Zoran Jovanovic f9a02500b6 [mips][microMIPS] Implement SWM16 and LWM16 instructions 
Differential Revision: http://reviews.llvm.org/D5579

llvm-svn: 222901
 2014-11-27 18:28:59 +00:00
Jozef Kolek 56a6a7d3bd [mips][microMIPS] Implement BREAK16 and SDBBP16 instructions 
Patch by Radovan Obradovic.

Differential Revision: http://reviews.llvm.org/D5048

llvm-svn: 222900
 2014-11-27 18:18:42 +00:00
Jozef Kolek e8c9d1eaf7 [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions 
Differential Revision: http://reviews.llvm.org/D5122

llvm-svn: 222653
 2014-11-24 14:39:13 +00:00
Zoran Jovanovic a4c4b5fc01 [mips][micromips] Implement SWM32 and LWM32 instructions 
Differential Revision: http://reviews.llvm.org/D5519

llvm-svn: 222367
 2014-11-19 16:44:02 +00:00
Jozef Kolek 5f95dd2b65 [mips][microMIPS] Implement LWXS instruction. 
Differential Revision: http://reviews.llvm.org/D5407

llvm-svn: 222348
 2014-11-19 11:39:12 +00:00
Jozef Kolek dc62fc4a8f [mips][microMIPS] Implement SDBBP and RDHWR instructions. 
Differential Revision: http://reviews.llvm.org/D5240

llvm-svn: 222347
 2014-11-19 11:25:50 +00:00
Zoran Jovanovic 8853171b46 [mips][microMIPS] Implement ANDI16 instruction 
llvm-svn: 221367
 2014-11-05 17:31:00 +00:00
Zoran Jovanovic a87308c84c Reverted revisions 221351, 221352 and 221353. 
llvm-svn: 221354
 2014-11-05 16:19:59 +00:00
Zoran Jovanovic e548bb0634 [mips][microMIPS] Implement ANDI16 instruction 
Differential Revision: http://reviews.llvm.org/D5163

llvm-svn: 221351
 2014-11-05 15:39:41 +00:00
Zoran Jovanovic 42b8444372 [mips][microMIPS] Implement ADDIUR1SP instruction 
Differential Revision: http://reviews.llvm.org/D5153

llvm-svn: 220477
 2014-10-23 11:13:59 +00:00
Zoran Jovanovic bac3619b29 ps][microMIPS] Implement ADDIUR2 instruction 
Differential Revision: http://reviews.llvm.org/D5151

llvm-svn: 220476
 2014-10-23 11:06:34 +00:00
Zoran Jovanovic 9bda2f1926 ps][microMIPS] Implement LI16 instruction 
Differential Revision: http://reviews.llvm.org/D5149

llvm-svn: 220475
 2014-10-23 10:59:24 +00:00
Zoran Jovanovic 4a00fdc2e3 [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D5774

llvm-svn: 220474
 2014-10-23 10:42:01 +00:00
Zoran Jovanovic 592239d498 [mips][microMIPS] Implement ADDU16 and SUBU16 instructions 
Differential Revision: http://reviews.llvm.org/D5118

llvm-svn: 220276
 2014-10-21 08:44:58 +00:00
Zoran Jovanovic 81ceebc56e [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D5117

llvm-svn: 220275
 2014-10-21 08:32:40 +00:00
Zoran Jovanovic 98bd58ca33 [mips][microMIPS] Implement ADDIUSP instruction 
Differential Revision: http://reviews.llvm.org/D5084

llvm-svn: 219500
 2014-10-10 14:37:30 +00:00
Zoran Jovanovic b26f889afa [mips][microMIPS] Implement ADDIUS5 instruction 
Differential Revision: http://reviews.llvm.org/D5049

llvm-svn: 219495
 2014-10-10 13:45:34 +00:00
Zoran Jovanovic c74e3eb9a6 [mips][microMIPS] Implement JRADDIUSP instruction 
Differential Revision: http://reviews.llvm.org/D5046

llvm-svn: 217681
 2014-09-12 14:29:54 +00:00
Zoran Jovanovic 4e7ac4ad2a [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions 
Differential Revision: http://reviews.llvm.org/D5211

llvm-svn: 217675
 2014-09-12 13:33:33 +00:00
Zoran Jovanovic 73ff948746 [mips][microMIPS] MicroMIPS Compact Branch Instructions BEQZC and BNEZC 
Differential Revision: http://reviews.llvm.org/D3545

llvm-svn: 215636
 2014-08-14 12:09:10 +00:00
Zoran Jovanovic cabf0f41e0 Implementation of 16-bit microMIPS instructions MFHI and MFLO. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3141

llvm-svn: 205532
 2014-04-03 12:47:34 +00:00
Zoran Jovanovic a0f5328984 Provide an operand for microMIPS wait instruction. 
llvm-svn: 204329
 2014-03-20 10:41:37 +00:00
Zoran Jovanovic 87d13e5ec1 Implementation of microMIPS 16-bit instructions MOVE and JALR. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3112

llvm-svn: 204325
 2014-03-20 10:18:24 +00:00
Zoran Jovanovic 7c6c36d92d Fixed encoding of SYSCALL microMIPS instruction. 
llvm-svn: 202523
 2014-02-28 18:17:08 +00:00
Zoran Jovanovic d0a289003d Revert revision 202518 because of wrong commit message. 
llvm-svn: 202521
 2014-02-28 18:14:16 +00:00