maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
31,887 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

6947 Commits

Author SHA1 Message Date
Bill Wendling 48a24419bf Updated. 
llvm-svn: 35352
 2007-03-26 07:55:58 +00:00
Bill Wendling 98d2104c6f Add support for the v1i64 type. This makes better code for this: 
#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

llvm-svn: 35351
 2007-03-26 07:53:08 +00:00
Anton Korobeynikov e8ac2fce97 Fix authorship 
llvm-svn: 35337
 2007-03-25 13:44:26 +00:00
Chris Lattner 26ad3e7191 add a note 
llvm-svn: 35334
 2007-03-25 05:10:46 +00:00
Chris Lattner 9c9e2f1af2 add a note 
llvm-svn: 35330
 2007-03-25 04:46:28 +00:00
Chris Lattner 8810241ebc Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll 
llvm-svn: 35329
 2007-03-25 04:44:03 +00:00
Chris Lattner d685514e2e switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Chris Lattner 927f30da08 Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. 
llvm-svn: 35320
 2007-03-25 02:01:03 +00:00
Chris Lattner 03a643aa69 enforce the proper range for the i386 N constraint. 
llvm-svn: 35319
 2007-03-25 01:57:35 +00:00
Chris Lattner c8ddca703d Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
llvm-svn: 35318
 2007-03-25 01:44:57 +00:00
Chris Lattner 43cab75914 add a bad case evan though of. 
llvm-svn: 35296
 2007-03-24 06:01:32 +00:00
Anton Korobeynikov 8aae2d7e1c Autodetect MMX & SSE stuff for AMD processors 
llvm-svn: 35292
 2007-03-23 23:46:48 +00:00
Bill Wendling 871c77cda1 PR1260: 
Add final support to get the QT example to compile.

llvm-svn: 35290
 2007-03-23 22:35:46 +00:00
Bill Wendling 7c17fbc5b7 We generate a shufflevector instruction, so we don't need the builtin 
intrinsic.

llvm-svn: 35269
 2007-03-22 20:29:26 +00:00
Bill Wendling d551a18783 Support added for shifts and unpacking MMX instructions. 
llvm-svn: 35266
 2007-03-22 18:42:45 +00:00
Dale Johannesen 0c6bb5eab7 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Anton Korobeynikov 4ad4bcdc2d Add TODO list for MSIL backend 
llvm-svn: 35244
 2007-03-21 21:48:59 +00:00
Anton Korobeynikov aa3090d815 Let the new backend begin! 
llvm-svn: 35242
 2007-03-21 21:38:25 +00:00
Dale Johannesen a827d03154 add generation of unnecessary push/pop around calls 
llvm-svn: 35241
 2007-03-21 21:16:39 +00:00
Nicolas Geoffray 4ea5217880 Protect R31's frame offset from being used by callee-saved registers, when R31 
is the frame pointer.

llvm-svn: 35233
 2007-03-21 16:44:14 +00:00
Evan Cheng 61eee86487 Mark re-materializable instructions. 
llvm-svn: 35230
 2007-03-21 00:16:56 +00:00
Evan Cheng cba9538499 Updated. 
llvm-svn: 35229
 2007-03-20 22:32:39 +00:00
Dale Johannesen bacf4acf65 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Lauro Ramos Venancio a88c4a74f3 bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Evan Cheng 9e7b838469 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng 39eb62ea3b New entry. 
llvm-svn: 35206
 2007-03-20 08:10:17 +00:00
Evan Cheng 61f39d186c Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Chris Lattner 3e1d917e80 Two changes: 
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204
 2007-03-20 06:08:29 +00:00
Chris Lattner f806e1cdbc fix indentation 
llvm-svn: 35202
 2007-03-20 02:25:53 +00:00
Dale Johannesen 8447d34903 fix obvious comment bug 
llvm-svn: 35196
 2007-03-20 00:30:56 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng ee2763f76f Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng 5be3e09a30 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng 461c964d3d Added isReMaterializable. 
llvm-svn: 35160
 2007-03-19 06:22:07 +00:00
Chris Lattner f01f87bc63 fix a warning 
llvm-svn: 35152
 2007-03-19 00:39:32 +00:00
Chris Lattner 9b3e2b4ad9 minor updates 
llvm-svn: 35143
 2007-03-18 22:41:33 +00:00
Nick Lewycky f764441977 This is implemented. We now generate: 
entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

llvm-svn: 35142
 2007-03-18 14:37:20 +00:00
Devang Patel b38c2ec89c Support 'I' inline asm constraint. 
llvm-svn: 35129
 2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio 25d4052af6 Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Bill Wendling 144b8bbf17 And now support for MMX logical operations. 
llvm-svn: 35125
 2007-03-16 09:44:46 +00:00
Evan Cheng 0e34d6af6b Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Bill Wendling e31034125c Multiplication support for MMX. 
llvm-svn: 35118
 2007-03-15 21:24:36 +00:00
Evan Cheng a1779b9739 Under X86-64 large code model, do not emit 32-bit pc relative calls. 
llvm-svn: 35108
 2007-03-14 22:11:11 +00:00
Evan Cheng 71face25ef Notes about codegen issues. 
llvm-svn: 35107
 2007-03-14 21:03:53 +00:00
Evan Cheng e278f30a52 Clean up. 
llvm-svn: 35105
 2007-03-14 20:20:19 +00:00
Evan Cheng eb76f7c6fd Oops. 
llvm-svn: 35104
 2007-03-14 19:44:58 +00:00
Evan Cheng dda4c32db3 X86-64 JIT is in large code model. Need stubs for direct calls. 
llvm-svn: 35097
 2007-03-14 10:51:55 +00:00
Evan Cheng 386dfc9251 x86-64 JIT stub codegen. 
llvm-svn: 35096
 2007-03-14 10:48:08 +00:00
Evan Cheng e1a95206e3 Preliminary support for X86-64 JIT stub codegen. 
llvm-svn: 35095
 2007-03-14 10:44:30 +00:00
Evan Cheng 72a8bcf238 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] 
llvm-svn: 35088
 2007-03-13 21:05:54 +00:00
Evan Cheng 507eefa757 Zero is always a legal AM immediate. 
llvm-svn: 35087
 2007-03-13 20:37:59 +00:00
Nicolas Geoffray 7aad92868c Stack and register alignment of call arguments in the ELF ABI 
llvm-svn: 35083
 2007-03-13 15:02:46 +00:00
Evan Cheng 818242bbaf Implement getTargetLowering() or else LSR won't be using ARM specific hooks. 
llvm-svn: 35077
 2007-03-13 01:20:42 +00:00
Evan Cheng 2150b9286f Updated TargetLowering LSR addressing mode hooks for ARM and Thumb. 
llvm-svn: 35075
 2007-03-12 23:30:29 +00:00
Evan Cheng b9dce9db85 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
llvm-svn: 35074
 2007-03-12 23:29:01 +00:00
Evan Cheng 3ab7ea7965 More flexible TargetLowering LSR hooks for testing whether an immediate is 
a legal target address immediate or scale.

llvm-svn: 35073
 2007-03-12 23:28:50 +00:00
Evan Cheng 57f261b13a Stupid bug: SSE2 supports v2i64 add / sub. 
llvm-svn: 35070
 2007-03-12 22:58:52 +00:00
Bill Wendling e9b81f5366 Adding more arithmetic operators to MMX. This is an almost exact copy of 
the addition. Please let me know if you have suggestions.

llvm-svn: 35055
 2007-03-10 09:57:05 +00:00
Evan Cheng 09663aeac7 Minor stuff. 
llvm-svn: 35049
 2007-03-09 19:46:06 +00:00
Evan Cheng 31ef0ab7cf Add comments about LSR / ARM. 
llvm-svn: 35048
 2007-03-09 19:35:33 +00:00
Evan Cheng 603f3094eb Unfinished work and ideas related to register scavenger. 
llvm-svn: 35047
 2007-03-09 19:34:51 +00:00
Dale Johannesen 368faf9acd apply comments from review of last patch 
llvm-svn: 35045
 2007-03-09 19:18:59 +00:00
Dale Johannesen af0cff2671 Add some observations from CoreGraphics benchmark. Remove register 
scavenging todo item, since it is now implemented.

llvm-svn: 35044
 2007-03-09 17:58:17 +00:00
Evan Cheng ea28fc5dc4 Implement inline asm modifier c. 
llvm-svn: 35035
 2007-03-08 22:42:46 +00:00
Bill Wendling 6092ce25cf Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that 
moves, loads, etc. are recognized.

llvm-svn: 35031
 2007-03-08 22:09:11 +00:00
Evan Cheng 63170b6959 Fix a typo. 
llvm-svn: 35030
 2007-03-08 21:59:30 +00:00
Evan Cheng ddf082082c Putting more constants which do not contain relocations into .literal{4|8|16} 
llvm-svn: 35026
 2007-03-08 08:31:54 +00:00
Evan Cheng e94a2f8026 Change register allocation order to Dale's suggestion. 
llvm-svn: 35021
 2007-03-08 02:56:40 +00:00
Evan Cheng 977195e912 Bug fix. Not advancing the register scavenger iterator correctly. 
llvm-svn: 35020
 2007-03-08 02:55:08 +00:00
Evan Cheng d918477ac3 For Darwin, put constant data into .const, .const_data, .literal{4|8|16} 
sections.

llvm-svn: 35017
 2007-03-08 01:25:25 +00:00
Evan Cheng 13a1d96963 Put constant data to .const, .const_data, .literal{4|8|16} sections. 
llvm-svn: 35016
 2007-03-08 01:07:07 +00:00
Evan Cheng 58aeb9c444 Add ReadOnlySection directive. 
llvm-svn: 35015
 2007-03-08 01:00:38 +00:00
Evan Cheng f030f2d628 Only safe to use a call-clobbered or spilled callee-saved register as scratch register. 
llvm-svn: 35010
 2007-03-07 20:30:36 +00:00
Bill Wendling 6d8211c0ac Remove useless pattern fragments. 
llvm-svn: 35009
 2007-03-07 18:23:09 +00:00
Anton Korobeynikov ed4b303c10 Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.

llvm-svn: 35008
 2007-03-07 16:25:09 +00:00
Bill Wendling 97905b4027 Properly support v8i8 and v4i16 types. It now converts them to v2i32 for 
load and stores.

llvm-svn: 35002
 2007-03-07 05:43:18 +00:00
Anton Korobeynikov 942fda027f Fix DWARF debugging information on x86/Linux and (hopefully) 
Mingw32/Cygwin targets. This fixes PR978

llvm-svn: 35000
 2007-03-07 02:47:57 +00:00
Evan Cheng 17cdad0687 ARM always use register scavenger. No longer reserves R12. 
llvm-svn: 34999
 2007-03-07 02:46:23 +00:00
Evan Cheng 2818fdd019 Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions. 
llvm-svn: 34998
 2007-03-07 02:38:05 +00:00
Evan Cheng 67038e7a8b Fix one more Thumb eliminateFrameIndex bug. 
llvm-svn: 34990
 2007-03-07 00:12:18 +00:00
Evan Cheng 5ed781b0db Register scavenging is now on by default for ARM. 
llvm-svn: 34987
 2007-03-06 22:02:53 +00:00
Evan Cheng 41bc2fd242 Make load / store optimizer use register scavenger. 
llvm-svn: 34986
 2007-03-06 21:59:20 +00:00
Bill Wendling bbd25984b7 Add LOAD/STORE support for MMX. 
llvm-svn: 34978
 2007-03-06 18:53:42 +00:00
Evan Cheng d28de6700b Code clean up. Prepare to use register scavenger. 
llvm-svn: 34976
 2007-03-06 18:02:41 +00:00
Evan Cheng 8b8cac289b Minor interface change. 
llvm-svn: 34967
 2007-03-06 10:05:14 +00:00
Evan Cheng 4783ae8ac1 Scavenge a register using the register scavenger when needed. 
llvm-svn: 34966
 2007-03-06 10:03:56 +00:00
Anton Korobeynikov e7ec3bc7bc Use new SDIselParamAttr enumeration. This removes "magick" constants 
from formal attributes' flags processing.

llvm-svn: 34963
 2007-03-06 08:12:33 +00:00
Chris Lattner 4f2e4e0f92 Switch PPC return lower to use an autogenerated CC description. 
llvm-svn: 34940
 2007-03-06 00:59:59 +00:00
Bill Wendling b1c86b49ea Add the emms intrinsic for MMX support. 
llvm-svn: 34938
 2007-03-05 23:09:45 +00:00
Lauro Ramos Venancio f10769dda7 Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS. 
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.

llvm-svn: 34931
 2007-03-05 17:59:58 +00:00
Jeff Cohen b622c11f77 Unbreak VC++ build. 
llvm-svn: 34917
 2007-03-05 00:00:42 +00:00
Chris Lattner d647f92a14 add missing braces 
llvm-svn: 34905
 2007-03-04 06:13:52 +00:00
Reid Spencer 1f87660d29 Make sure that when we store a value it is masked to its correct bit 
width. This helps CBE work with non-standard integer bit widths.

llvm-svn: 34885
 2007-03-03 16:33:33 +00:00
Nick Lewycky e6049c2f08 Emit low/high immediate loads properly for Linux/PPC. 
llvm-svn: 34871
 2007-03-03 05:29:51 +00:00
Evan Cheng deaea25eb9 X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8* }. 
llvm-svn: 34857
 2007-03-02 23:16:35 +00:00
Anton Korobeynikov 57af2a4f3b Simplify things 
llvm-svn: 34849
 2007-03-02 21:50:27 +00:00
Chris Lattner 9c7e5e365d argument lowering should copy from the vreg shadows of live-in arguments 
passed in registers, not directly from the pregs themselves.

llvm-svn: 34838
 2007-03-02 05:12:29 +00:00
Chris Lattner fc2f52128a add a note 
llvm-svn: 34837
 2007-03-02 05:04:52 +00:00
Dale Johannesen 32bc81341b eliminate unnecessary reset of SP in epilog on darwin 
llvm-svn: 34824
 2007-03-02 01:17:17 +00:00
Reid Spencer df30e2a68b Wrap a long line. 
llvm-svn: 34799
 2007-03-01 19:48:16 +00:00
Anton Korobeynikov af8be4458f Ensure that fastcall'ed function is correctly mangled & stack is 
properly aligned

llvm-svn: 34788
 2007-03-01 16:29:22 +00:00
Nicolas Geoffray 75ab9799df Implemented the frameaddress intrinsic for PPC. 
llvm-svn: 34787
 2007-03-01 13:11:38 +00:00
Evan Cheng 2c0fd3ee4c Use a spilled free callee-saved register as scratch register. 
llvm-svn: 34785
 2007-03-01 08:57:52 +00:00
Evan Cheng 6f059e3e0a - Track which callee-saved registers are spilled. 
- Some code clean up.

llvm-svn: 34783
 2007-03-01 08:26:31 +00:00
Evan Cheng 677bb3b460 Switch from std::vector<bool> to BitVector. 
llvm-svn: 34781
 2007-03-01 07:52:44 +00:00
Bill Wendling 65c75b57d4 Get rid of verboten <iostream> include. 
llvm-svn: 34777
 2007-03-01 06:05:39 +00:00
Dale Johannesen 962fa8eb9a Changes requested in review of last pass. Also pulled isThumb into a 
member, instead of resetting in every function that uses it.

llvm-svn: 34764
 2007-02-28 23:20:38 +00:00
Evan Cheng f6ca943638 Doh. ARM::PC is obvious a reserved register. 
llvm-svn: 34763
 2007-02-28 23:12:34 +00:00
Dale Johannesen 440995bd9a Add intelligence about where to break large blocks. 
llvm-svn: 34755
 2007-02-28 18:41:23 +00:00
Chris Lattner 7373f3a351 remove dead option 
llvm-svn: 34754
 2007-02-28 18:39:53 +00:00
Chris Lattner eb09e28ccc bugfix: fastcall does not require the first two params to be marked 'inreg', 
they always get registers.

llvm-svn: 34748
 2007-02-28 18:35:11 +00:00
Nate Begeman e0232ec706 More Mach-O writer improvements. 
llvm-svn: 34740
 2007-02-28 07:40:50 +00:00
Chris Lattner 152bfa103e use high-level functions in CCState 
llvm-svn: 34739
 2007-02-28 07:09:55 +00:00
Chris Lattner 227b6c5d19 make use of helper functions in CCState for analyzing formals and calls. 
llvm-svn: 34737
 2007-02-28 07:00:42 +00:00
Chris Lattner d439e86078 switch LowerFastCCCallTo over to using the new fastcall description. 
llvm-svn: 34734
 2007-02-28 06:26:33 +00:00
Chris Lattner 66e1d1dd7e switch LowerFastCCArguments over to using the autogenerated Fastcall description. 
llvm-svn: 34733
 2007-02-28 06:21:19 +00:00
Chris Lattner 0bc74fd6cc add new CC_X86_32_FastCall calling conv, which describes fastcall on win32. 
Factor out a CC_X86_32_Common convention, which is the part shared between
ccc, stdcall and fastcall

llvm-svn: 34732
 2007-02-28 06:20:01 +00:00
Chris Lattner 3066beccb5 rearrange code 
llvm-svn: 34731
 2007-02-28 06:10:12 +00:00
Chris Lattner 3ed3be3b4a remove fastcc (not fastcall) support 
llvm-svn: 34730
 2007-02-28 06:05:16 +00:00
Chris Lattner b9db225049 switch LowerCCCArguments over to using autogenerated CC. 
llvm-svn: 34729
 2007-02-28 05:46:49 +00:00
Chris Lattner 5958b176f3 simplify sret handling 
llvm-svn: 34728
 2007-02-28 05:39:26 +00:00
Chris Lattner be7995953a switch LowerCCCCallTo over to using an autogenerated callingconv 
llvm-svn: 34727
 2007-02-28 05:31:48 +00:00
Chris Lattner 0c0a7b288e rename stuff 
llvm-svn: 34726
 2007-02-28 05:30:29 +00:00
Chris Lattner 6f287c6e92 rename some CCActions, add CCIfInReg 
llvm-svn: 34725
 2007-02-28 05:29:33 +00:00
Chris Lattner ba3d273122 switch return value passing and the x86-64 calling convention information 
over to being autogenerated from the X86CallingConv.td file.

llvm-svn: 34722
 2007-02-28 04:55:35 +00:00
Chris Lattner 659ca56383 make subtarget references work. 
llvm-svn: 34721
 2007-02-28 04:51:41 +00:00
Evan Cheng e8af69632f Make requiresRegisterScavenging determination on a per MachineFunction basis. 
llvm-svn: 34711
 2007-02-28 00:59:19 +00:00
Evan Cheng 9049cd72e6 Temporary: make R12 available in ARM mode if RegScavenger is being used. 
llvm-svn: 34709
 2007-02-28 00:22:44 +00:00
Evan Cheng 30508919c8 Start making use of RegScavenger. 
llvm-svn: 34708
 2007-02-28 00:21:58 +00:00
Evan Cheng 95ae95a6a6 PEI now passes a RegScavenger ptr to eliminateFrameIndex. 
llvm-svn: 34707
 2007-02-28 00:21:17 +00:00
Evan Cheng ee8aca0cfa Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function. 
llvm-svn: 34701
 2007-02-27 23:03:55 +00:00
Chris Lattner c5e2a3a80e reenable generation of CC info 
llvm-svn: 34699
 2007-02-27 22:12:19 +00:00
Evan Cheng 6f0969ecb9 Back out previous commit temporarily. 
llvm-svn: 34694
 2007-02-27 21:47:22 +00:00
Evan Cheng 71a7271b8b Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info. 
llvm-svn: 34692
 2007-02-27 21:12:35 +00:00
Chris Lattner aeb9ebe3cf implement CCMatchIfCC in terms of CCMatchIf 
llvm-svn: 34685
 2007-02-27 20:45:02 +00:00
Chris Lattner 98c9bd586e build cc info 
llvm-svn: 34684
 2007-02-27 20:44:31 +00:00
Chris Lattner 2ebb2e99d1 a note 
llvm-svn: 34670
 2007-02-27 17:21:09 +00:00
Nicolas Geoffray b524dfd557 Fix parenthesis for BCTRL_{ELF|Macho} test. 
llvm-svn: 34668
 2007-02-27 13:10:41 +00:00
Nicolas Geoffray 89d81878d2 Differentiate between the MachO and the ELF ABI the CALL instruction. 
llvm-svn: 34667
 2007-02-27 13:01:19 +00:00
Jim Laskey b6e200bd68 Duplicate use of LR, take 2. 
llvm-svn: 34666
 2007-02-27 11:55:45 +00:00
Chris Lattner fa9227ed54 Add calling convention info 
llvm-svn: 34661
 2007-02-27 06:59:52 +00:00
Chris Lattner db2049fb8e move target independent calling convention stuff to TargetCallingConv.td 
llvm-svn: 34659
 2007-02-27 05:57:32 +00:00
Chris Lattner 4c83b98604 fill in some holes 
llvm-svn: 34658
 2007-02-27 05:51:05 +00:00
Chris Lattner c9eed39a5d switch x86-64 return value lowering over to using same mechanism as argument 
lowering uses.

llvm-svn: 34657
 2007-02-27 05:28:59 +00:00
Chris Lattner 9f059194a7 Minor refactoring of CC Lowering interfaces 
llvm-svn: 34656
 2007-02-27 05:13:54 +00:00
Chris Lattner dc3adc83e7 move CC Lowering stuff to its own public interface 
llvm-svn: 34655
 2007-02-27 04:43:02 +00:00
Chris Lattner 2e5e8407ad refactor x86-64 argument lowering yet again, this time eliminating templates, 
'clients', etc, and adding CCValAssign instead.

llvm-svn: 34654
 2007-02-27 04:18:15 +00:00
Evan Cheng 5d7ce57c13 Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping 
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.h updated: 1.28 -> 1.29

llvm-svn: 34652
 2007-02-27 02:55:29 +00:00
Chris Lattner 535bd6d3ba always lower to RETFLAG, never leave it as just ret. 
llvm-svn: 34639
 2007-02-26 19:44:02 +00:00
Chris Lattner 77f0a1553c fix attribution 
llvm-svn: 34637
 2007-02-26 18:56:07 +00:00