3395d4485d
CellSPU: Ensure that C strings are always put in the .rodata section
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llvm-svn: 58839
2008-11-07 11:06:44 +00:00
ca08e0645a
Add XCore backend.
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llvm-svn: 58838
2008-11-07 10:59:00 +00:00
7095cd2af2
Jump table JIT support. Work in progress.
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llvm-svn: 58836
2008-11-07 09:06:08 +00:00
34d93f8572
Teach CellSPU about ELF sections and new section emitter classes.
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NB: This is likely to need more work.
llvm-svn: 58832
2008-11-07 04:36:25 +00:00
98dc53e926
Encode misc arithmetic instructions.
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llvm-svn: 58828
2008-11-07 01:41:35 +00:00
49d665218c
Encode extend instructions; more clean up.
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llvm-svn: 58818
2008-11-06 22:15:19 +00:00
aa03cd3336
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
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- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
47b546d75f
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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llvm-svn: 58800
2008-11-06 08:47:38 +00:00
9a8d60a7c0
Widening cleanup
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llvm-svn: 58796
2008-11-06 05:31:54 +00:00
36ae40342f
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
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llvm-svn: 58793
2008-11-06 03:35:07 +00:00
b870fd8874
Fix so_imm encoding bug; add support for MOVi2pieces.
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llvm-svn: 58790
2008-11-06 02:25:39 +00:00
2686c8fb34
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
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llvm-svn: 58789
2008-11-06 01:21:28 +00:00
fd2adbfa28
Encode pic load / store instructions; fix some encoding bugs.
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llvm-svn: 58780
2008-11-05 23:22:34 +00:00
81889d010c
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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llvm-svn: 58764
2008-11-05 18:35:52 +00:00
7a638a8c7e
Reintroduce a comment that was removed with the AddToISelQueue
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changes.
llvm-svn: 58760
2008-11-05 17:16:24 +00:00
bfd58d87f3
Test commit, add Makefile for XCore target, more to follow.
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llvm-svn: 58755
2008-11-05 09:53:58 +00:00
27889ab29f
Add more vector move low and zero-extend patterns.
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llvm-svn: 58752
2008-11-05 06:04:51 +00:00
3cd5e8c97b
Indentation.
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llvm-svn: 58750
2008-11-05 06:03:38 +00:00
f14b77ebf1
Eliminate the ISel priority queue, which used the topological order for a
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priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
llvm-svn: 58748
2008-11-05 04:14:16 +00:00
fd820528ab
Use getTargetConstant instead of getConstant for nodes that should not be visited
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by isel and potentially forced into registers.
llvm-svn: 58747
2008-11-05 02:06:09 +00:00
132de1983f
Rename isGVLazyPtr to isGVNonLazyPtr relocation. This represents Mac OS X
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indirect gv reference. Please don't call it lazy.
llvm-svn: 58746
2008-11-05 01:50:32 +00:00
e3827d9061
Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
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llvm-svn: 58725
2008-11-04 22:19:55 +00:00
297b32a367
Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
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llvm-svn: 58714
2008-11-04 19:57:48 +00:00
4eaff40147
Debug output tweak.
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llvm-svn: 58708
2008-11-04 17:58:53 +00:00
453844c352
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
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llvm-svn: 58707
2008-11-04 17:57:07 +00:00
9340be4641
For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.
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This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.
llvm-svn: 58688
2008-11-04 09:30:48 +00:00
2299c99d79
Stylistic change.
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llvm-svn: 58683
2008-11-04 06:10:06 +00:00
6dd08b6604
Handle ARM machine constantpool entries.
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llvm-svn: 58671
2008-11-04 00:50:32 +00:00
b9110e7fbb
The ANDMask node folds to a constant, and isn't the node that needs to
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have its node id set. The new and and shift nodes are the nodes that need
the IDs. This fixes PR2982.
llvm-svn: 58655
2008-11-03 23:43:55 +00:00
f60e5aaaac
Remove a dead switch statement.
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llvm-svn: 58644
2008-11-03 21:26:52 +00:00
3620e685b5
Minor code restructuring. No functionality change.
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llvm-svn: 58643
2008-11-03 21:02:39 +00:00
4d0549e3be
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
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llvm-svn: 58626
2008-11-03 18:38:31 +00:00
ac41d9f5d8
Refactor various TargetAsmInfo subclasses' TargetMachine members away
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adding a TargetMachine member to the base TargetAsmInfo class instead.
llvm-svn: 58624
2008-11-03 18:22:42 +00:00
03f5122c6c
Whitespace fixes. No functionality change.
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llvm-svn: 58539
2008-10-31 21:26:08 +00:00
83bf3de134
Add comment.
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llvm-svn: 58533
2008-10-31 19:56:03 +00:00
20dbb3bcad
Use better data structure for ConstPoolId2AddrMap.
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llvm-svn: 58532
2008-10-31 19:55:13 +00:00
44994e0c77
Actually make debug output understandable.
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llvm-svn: 58529
2008-10-31 19:15:52 +00:00
ef89465c9f
x86_64 rip-relative and magic mode address
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llvm-svn: 58528
2008-10-31 19:13:42 +00:00
8fce66a47c
Forgot this in last commit.
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llvm-svn: 58527
2008-10-31 19:11:09 +00:00
467e6e8093
Encode PICADD; some code clean up.
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llvm-svn: 58526
2008-10-31 19:10:44 +00:00
d2bc13380f
Revert r58489. It isn't correct for all cases.
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llvm-svn: 58523
2008-10-31 18:30:19 +00:00
7e8202fce4
Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm.
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llvm-svn: 58517
2008-10-31 16:52:57 +00:00
6d70df0b05
Don't skip over all "terminator" instructions when determining where to put the
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callee-saved restore code. It could skip over conditional jumps
accidentally. Instead, just skip the "return" instructions.
llvm-svn: 58489
2008-10-31 04:00:23 +00:00
99cdf8893e
Use MOVSSmr instead of EXTRACTPSmr in the case of extracting
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vector element 0 for a store, as it's smaller and faster.
llvm-svn: 58483
2008-10-31 00:57:24 +00:00
c696ef9b11
I think we got non-machine specific constpool entries covered.
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llvm-svn: 58474
2008-10-30 23:43:36 +00:00
1310574b0f
Shift amounts should have type getShiftAmountTy
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(i32 for PPC, not i8). Correct this, and some
formatting while there.
llvm-svn: 58451
2008-10-30 19:28:32 +00:00
0852f48d1d
Shift amounts should have the type given by
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getShiftAmountTy (i32 in the case of CellSPU).
llvm-svn: 58449
2008-10-30 19:24:28 +00:00
66cff408ff
ARM JIT should observe -relocation-model command line option.
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llvm-svn: 58433
2008-10-30 16:10:54 +00:00
58c3794c27
Add initial support for vector widening. Logic is set to widen for X86.
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One will only see an effect if legalizetype is not active. Will move
support to LegalizeType soon.
llvm-svn: 58426
2008-10-30 08:01:45 +00:00
487c43412d
Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stack
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so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU.
N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is
still unexorcised code.
llvm-svn: 58415
2008-10-30 01:51:48 +00:00
Scott Michel