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18 Commits

Author SHA1 Message Date
Simon Dardis 65b0492f0d [mips] Correct the predicates of sign extension instructions 
And eliminatw the duplication of those instructions for microMIPS32r6.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46117

llvm-svn: 331526
 2018-05-04 15:00:54 +00:00
Simon Dardis 694fde215e Revert "[mips] Correct the predicates of sign extension instructions" 
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.

This reverts r331346.

llvm-svn: 331348
 2018-05-02 12:35:29 +00:00
Simon Dardis 7a36495bf7 [mips] Correct the predicates of sign extension instructions 
And eliminate the duplication of those instructions for microMIPS32r6.

llvm-svn: 331346
 2018-05-02 12:25:33 +00:00
Simon Dardis 6cfc9ba5e3 [mips] Correct the predicates for shifts. 
Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46123

llvm-svn: 331341
 2018-05-02 09:55:49 +00:00
Simon Dardis eac9301cdb [mips] Fix the definition of sync, synci 
Also, fix the disassembly of synci for microMIPS.

Reviewers: abeserminji, smaksimovic, atanasyan

Differential Revision: https://reviews.llvm.org/D45870

llvm-svn: 330810
 2018-04-25 10:19:22 +00:00
Simon Dardis 476ed8f26e [mips] Fix the definitions of the EVA instructions 
Correct their availability to their respective ISAs.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D44209

llvm-svn: 327403
 2018-03-13 14:39:44 +00:00
Stefan Maksimovic b3e7ed3b94 [mips] Define certain instructions in microMIPS32r3 
Instructions affected:
mthc1, mfhc1, add.d, sub.d, mul.d, div.d,
mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d

These instructions are now defined for
microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td
since they shared their encoding with those already defined
in microMIPS32r6InstrInfo.td and have been therefore
removed from the latter file.

Some instructions present in MicroMipsInstrFPU.td which
did not have both AFGR64 and FGR64 variants defined have
been altered to do so.

Differential revision: https://reviews.llvm.org/D42738

llvm-svn: 324584
 2018-02-08 09:25:17 +00:00
Stefan Maksimovic 98749e0249 [mips] Properly select abs and sqrt instructions 
- Alter abs for micromips to have both AFGR64 and FGR64
  variants, same as sqrt
- Remove sqrt and abs from MicroMips32r6InstrInfo.td,
  use micromips FGR64 variants
- Restrict non-micromips abs/sqrt with NotInMicroMips
  predicate

Differential revision: https://reviews.llvm.org/D41439

llvm-svn: 323184
 2018-01-23 10:09:39 +00:00
Simon Dardis b633acac9f [mips] Fix (dis)assembly of abs.fmt for micromips 
These instructions were previously marked as codegen only preventing
them from being assembled as microMIPS or disassembled.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D39123

llvm-svn: 316656
 2017-10-26 11:36:54 +00:00
Simon Dardis 0d378a9eed [mips][micromips] Fix (dis)assembly of bc1(t|f) 
Previously these instructions were marked codegen only and had
an under-specified instruction description that did not record the
fcc register.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D38847

llvm-svn: 315905
 2017-10-16 14:20:22 +00:00
Simon Dardis 730fdb73a1 [mips] Correct c.cond.fmt instruction definition. 
Permit explicit $fcc<X> operand in c.cond.fmt instruction.

Add c.cond.fmt to the MIPS to microMIPS instruction mapping table.

Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for
c.cond.fmt, bc1t, bc1f.

Reviewers: seanbruno, zoran.jovanovic, vkalintiris

Differential Revision: https://reviews.llvm.org/D24510

llvm-svn: 292117
 2017-01-16 13:55:58 +00:00
Simon Dardis 6efb8dd2e3 [mips] seb, seh instruction aliases 
Add the single operand form.

Reviewers: vkalintiris

Differential Revision: https://reviews.llvm.org/D26961

llvm-svn: 287681
 2016-11-22 19:17:23 +00:00
Simon Dardis 7b7cb8d9dd [mips] not instruction alias 
This patch adds the single operand form of the not alias to microMIPS and
MIPS along with additional tests.

This partially resolves PR/30381.

Thanks to Sean Bruno for reporting the issue!

llvm-svn: 287097
 2016-11-16 11:04:49 +00:00
Simon Dardis 9c34854833 [mips] synci microMIPS instruction definition. 
Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci
as not being part of microMIPS. This does not cover the sync instruction alias,
as that will be handled with a different patch. Add sync to the valid tests for
microMIPS.

Reviewers: vkalintiris

Differential Revision: https://reviews.llvm.org/D25795

llvm-svn: 284962
 2016-10-24 10:23:59 +00:00
Simon Dardis f45a59f80b Recommit: "[mips] Add rsqrt, recip for MIPS" 
Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.

Reviewers: vkalintiris, zoran.jovanoic

Differential Review: https://reviews.llvm.org/D24499

llvm-svn: 283334
 2016-10-05 16:11:01 +00:00
Simon Dardis bbfd528748 Revert "[mips] Add rsqrt, recip for MIPS" 
This reverts commit r282485 which contain two patches instead of
one.

llvm-svn: 283327
 2016-10-05 15:28:33 +00:00
Simon Dardis 0486d585c5 [mips] Add rsqrt, recip for MIPS 
Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.

Reviewers: vkalintiris, zoran.jovanoic

Differential Review: https://reviews.llvm.org/D24499

llvm-svn: 282485
 2016-09-27 12:25:15 +00:00
Hrvoje Varga 846bdb746d [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions 
Differential Revision: https://reviews.llvm.org/D22347

llvm-svn: 277719
 2016-08-04 11:22:52 +00:00