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14 Commits

Author SHA1 Message Date
Simon Pilgrim 781dece55e Don't repeatedly evaluate size() in the for loop. NFCI. 
llvm-svn: 329853
 2018-04-11 22:24:48 +00:00
Craig Topper 40d3b32e12 [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD 
This makes the Y position consistent with other instructions.

This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary.

llvm-svn: 328254
 2018-03-22 21:55:20 +00:00
Craig Topper df99baa4df [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 
Bits 7:4 control the scale part of the operation. If the scale is 0 the behavior is equivalent to VROUND.

Fixes PR36246

llvm-svn: 324985
 2018-02-13 04:19:26 +00:00
Craig Topper e5d44cefea [X86] Teach EVEX->VEX pass to turn SHUFI32X4/SHUFF32X4/SHUFI64X/SHUFF64X2 into VPERM2F128/VPERM2I128. 
This recovers some of the tests that were changed by r317403.

llvm-svn: 317410
 2017-11-04 18:10:03 +00:00
Craig Topper 4e56ba271e [X86] Add custom code to EVEX to VEX pass to turn unmasked 128-bit VPALIGND/Q into VPALIGNR if the extended registers aren't being used. 
This will enable us to prefer VALIGND/Q during shuffle lowering in order to get the extended register encoding space when BWI isn't available. But if we end up not using the extended registers we can switch VPALIGNR for the shorter VEX encoding.

Differential Revision: https://reviews.llvm.org/D39401

llvm-svn: 317122
 2017-11-01 21:00:59 +00:00
Craig Topper 485cca1ecb [AVX512] Add 128->256 vbroadcastf64x2/vbroadcasti64x2 instructions to the EVEX->VEX table. 
llvm-svn: 311307
 2017-08-21 05:03:28 +00:00
Benjamin Kramer dd0620ed97 Another instance where GCC doesn't understand implicit construction of StringLiteral. 
llvm-svn: 298703
 2017-03-24 14:17:56 +00:00
Benjamin Kramer 46f5e2c47b Make GCC happy again. 
llvm-svn: 298702
 2017-03-24 14:15:35 +00:00
Benjamin Kramer c06d672a7a Don't build up std::vectors with constant sizes when an array suffices. 
NFC.

llvm-svn: 298701
 2017-03-24 14:11:47 +00:00
Craig Topper bb4089d260 Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead." 
This reverts r297596.

There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table.

llvm-svn: 297602
 2017-03-13 05:34:03 +00:00
Craig Topper 166085f0f2 [AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead. 
This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch.

llvm-svn: 297596
 2017-03-13 00:36:49 +00:00
Craig Topper 9fc4135cc2 [X86] Minor formatting tweaks in EVEX to VEX tables. NFC 
llvm-svn: 297595
 2017-03-13 00:36:46 +00:00
Ayman Musa 63cfb16b93 [X86] Quick fix for build bot failure (r297127) due to unused variable. 
llvm-svn: 297130
 2017-03-07 08:56:27 +00:00
Ayman Musa 850fc977c8 [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables. 
X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible.
It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals.
This TableGen backend replaces the tables by automatically generating them.

Differential Revision: https://reviews.llvm.org/D30451

llvm-svn: 297127
 2017-03-07 08:11:19 +00:00