Commit Graph

274 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 2608157f79 Use an existing function.
llvm-svn: 145883
2011-12-06 00:51:12 +00:00
Owen Anderson 3543398bcf There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
llvm-svn: 139531
2011-09-12 20:07:22 +00:00
Owen Anderson 93cd31869b Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
llvm-svn: 139429
2011-09-09 23:05:14 +00:00
Owen Anderson 29cfe6c368 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
Owen Anderson 64d53620aa Re-apply r135319 with a fix for the constant island pass.
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414
2011-07-18 18:50:52 +00:00
Jim Grosbach 7471937ad7 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746
2011-07-08 21:50:04 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Evan Cheng 88530e6568 Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
llvm-svn: 128743
2011-04-01 22:09:28 +00:00
Duncan Sands 75b5d27b84 Spelling fix: consequtive -> consecutive.
llvm-svn: 125563
2011-02-15 09:23:02 +00:00
Owen Anderson 4ebf471c9b Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
llvm-svn: 125127
2011-02-08 22:39:40 +00:00
Evan Cheng 558ccef74f Temporary workaround for a bad bug introduced by r121082 which replaced
t2LDRpci with t2LDRi12.
There are a couple of problems with this.
1. The encoding for the literal and immediate constant are different.
   Note bit 7 of the literal case is 'U' so it can be negative.
2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run.
   So we end up never using the Thumb2 instruction, which ends up creating a
   lot more constant islands.

llvm-svn: 125074
2011-02-08 03:07:03 +00:00
Anton Korobeynikov 221f4faa92 Save a mapping between original and cloned constpool entries.
llvm-svn: 124570
2011-01-30 22:07:39 +00:00
Evan Cheng dfce83c8f5 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
2011-01-17 08:03:18 +00:00
Bill Wendling 18581a4ac0 Comment cleanups.
llvm-svn: 122302
2010-12-21 01:54:40 +00:00
Bill Wendling a4dda53686 RemoveUnusedCPEntries can change things. Track it.
llvm-svn: 122129
2010-12-18 01:53:06 +00:00
Jim Grosbach bfef309d11 Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.

llvm-svn: 121920
2010-12-15 23:52:36 +00:00
Owen Anderson 9a4d42855d Revert r121721, which broke buildbots.
llvm-svn: 121726
2010-12-13 22:51:08 +00:00
Owen Anderson 4efa445f3c Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

llvm-svn: 121721
2010-12-13 22:29:52 +00:00
Jim Grosbach 327cf8ee5f Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
possible. They were duplicates for everything exception the source pattern
before.

llvm-svn: 121179
2010-12-07 20:41:06 +00:00
Owen Anderson 99ea8a3510 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
llvm-svn: 121082
2010-12-07 00:45:21 +00:00
Jim Grosbach 81af4f9eb1 Rename t2 TBB and TBH instructions to reference that they encode the jump table
data. Next up, pseudo-izing them.

llvm-svn: 120320
2010-11-29 21:28:32 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
2010-10-26 22:37:02 +00:00
Eric Christopher 8a70781cac Remove extra header.
llvm-svn: 111456
2010-08-18 23:38:16 +00:00
Evan Cheng 44a320dafa Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637
llvm-svn: 110947
2010-08-12 20:30:05 +00:00
Evan Cheng ce8fb68078 Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations.
llvm-svn: 110584
2010-08-09 18:35:19 +00:00
Owen Anderson a7aed18624 Reapply r110396, with fixes to appease the Linux buildbot gods.
llvm-svn: 110460
2010-08-06 18:33:48 +00:00
Owen Anderson bda59bd247 Revert r110396 to fix buildbots.
llvm-svn: 110410
2010-08-06 00:23:35 +00:00
Owen Anderson 755aceb5d0 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
2010-08-05 23:42:04 +00:00
Dale Johannesen c17dd5790b Revert 109076. It is wrong and was causing regressions. Add some
comments explaining why it was wrong.  8225024.

Fix the real problem in 8213383: the code that splits very large
blocks when no other place to put constants can be found was not
considering the case that the block contained a Thumb tablejump.

llvm-svn: 109282
2010-07-23 22:50:23 +00:00
Chris Lattner 749ca32da1 eliminate the TargetInstrInfo::GetInstSizeInBytes hook.
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.

llvm-svn: 109171
2010-07-22 21:27:00 +00:00
Evan Cheng 3fabe07d4c Fix constant island pass's handling of tBR_JTr. The offset of the instruction does not have to be 4-byte aligned. Rather, it's the offset + 2 that must be aligned since the instruction expands into:
mov     pc, r1
        .align  2
LJTI0_0_0:
        .long    LBB0_14

This fixes rdar://8213383. No test case since it's not possible to come up with a suitable small one.

llvm-svn: 109076
2010-07-22 02:09:47 +00:00
Jim Grosbach 73ef80f76f grammar
llvm-svn: 107831
2010-07-07 22:53:35 +00:00
Jim Grosbach 40eda1076a Handle cases where the post-RA scheduler may move instructions between the
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682

llvm-svn: 107830
2010-07-07 22:51:22 +00:00
Jim Grosbach e4ba2aa0c4 grammar and trailing whitespace
llvm-svn: 107811
2010-07-07 21:06:51 +00:00
Dan Gohman d2d1ae105d Use pre-increment instead of post-increment when the result is not used.
llvm-svn: 106542
2010-06-22 15:08:57 +00:00
Jim Grosbach 97c8a6a928 early exit for dbg_value instructions
llvm-svn: 106430
2010-06-21 17:49:23 +00:00
Jim Grosbach 84511e1526 Clean up 80 column violations. No functional change.
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Chris Lattner 6f306d7d30 use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
llvm-svn: 100214
2010-04-02 20:16:16 +00:00
Bob Wilson 947f04bad0 Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409
2010-03-13 01:08:20 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Chris Lattner feba1e2495 eliminate the ARMFunctionInfo::Align member, using
MachineFunction::Alignment instead.

llvm-svn: 94701
2010-01-27 23:37:36 +00:00
Chris Lattner a14ac3fd80 prep work to support a future where getJumpTableInfo will return
a null pointer for functions with no jump tables.  No functionality
change.

llvm-svn: 94469
2010-01-25 23:22:00 +00:00
Chris Lattner a48f44d9ee improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!

llvm-svn: 90365
2009-12-03 00:50:42 +00:00
Jim Grosbach 6c3b71195a The verify() call of CPEIsInRange() isn't right for the assertion check of
constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.

llvm-svn: 89473
2009-11-20 19:37:38 +00:00
Jim Grosbach fc81352e3f Remove verifySizes() since it's not adding much value.
llvm-svn: 89443
2009-11-20 02:32:06 +00:00
Jim Grosbach b73918c42d When placing constant islands and adjusting for alignment padding, inline
assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.

llvm-svn: 89403
2009-11-19 23:10:28 +00:00
Jim Grosbach 36a5bf82bf fix typo
llvm-svn: 89369
2009-11-19 18:23:19 +00:00
Jim Grosbach cdde77c6a3 Enable arm jumpt table adjustment.
llvm-svn: 89143
2009-11-17 21:24:11 +00:00
Jim Grosbach af1ad30a23 When moving a block for table jumps, make sure the prior block terminator
is analyzable so it can be updated. If it's not, be safe and don't move the
block.

llvm-svn: 89022
2009-11-17 01:21:04 +00:00
Jim Grosbach 9785e5914f Simplify thumb2 jump table adjustments. Remove unnecessary calculation and
usage of block sizes and offsets.

llvm-svn: 88935
2009-11-16 18:58:52 +00:00
Jim Grosbach 87b0f0d95c clarify comment
llvm-svn: 88933
2009-11-16 18:55:47 +00:00
Jim Grosbach 9c148c2163 back off for a bit. tracking down weirdness
llvm-svn: 88919
2009-11-16 17:17:48 +00:00
Jim Grosbach 47d5e333ff Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior.
llvm-svn: 88917
2009-11-16 17:10:56 +00:00
Jim Grosbach e07594df45 cleanup.
llvm-svn: 88812
2009-11-14 21:33:37 +00:00
Jim Grosbach 43d2108546 Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB.
llvm-svn: 88805
2009-11-14 20:10:18 +00:00
Jim Grosbach 46a524c3e8 Block renumbering
llvm-svn: 87056
2009-11-13 01:19:24 +00:00
Jim Grosbach 5d57714e6c Update TB[BH] layout optimization. Add support for moving the target block
to directly follow the jump table. Move the layout changes to prior to any
constant island handling.

llvm-svn: 86999
2009-11-12 17:25:07 +00:00
Jim Grosbach 6385ea7c4e Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway.
llvm-svn: 86945
2009-11-12 03:28:35 +00:00
Jim Grosbach d576d66d91 Do jump table adjustment before constant island allocation
llvm-svn: 86857
2009-11-11 19:04:24 +00:00
Jim Grosbach 8d92ec45c7 The TBB and TBH instructions for Thumb2 are really handy for jump tables, but
can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.

llvm-svn: 86791
2009-11-11 02:47:19 +00:00
Jim Grosbach d7cf55cd0e Use Unified Assembly Syntax for the ARM backend.
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
Evan Cheng 6f29ad9170 Use cbz and cbnz instructions.
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
Nick Lewycky 974e12b2d3 Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
2009-10-25 06:57:41 +00:00
Nick Lewycky 02d5f77d26 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
2009-10-25 06:33:48 +00:00
Bob Wilson 2f9be50774 Fix a potential performance problem in placing ARM constant pools.
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references.  This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.

llvm-svn: 84202
2009-10-15 20:49:47 +00:00
Bob Wilson 68ead6c7a8 Be smarter about reusing constant pool entries.
llvm-svn: 84173
2009-10-15 05:52:29 +00:00
Bob Wilson b4f2a85fe4 Fix another problem with ARM constant pools. Radar 7303551.
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them.  My recent change exposed a problem in this area.  We may
sometimes append to the same block more than one unconditional branch.  The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.

This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before.  The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block.  The insertion point could be out of range.  When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.

The fix is to only append an unconditional branch if the block does not
already end with one.  I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.

There is more to be done here, but I think this fixes the immediate problem.

llvm-svn: 84172
2009-10-15 05:10:36 +00:00
Bob Wilson d26a26ae7e Fix regression introduced by r83894.
llvm-svn: 83982
2009-10-13 17:29:13 +00:00
Bob Wilson 5b07a903d4 Delete a comment that makes no sense to me. The statement that moving a CPE
before its reference is only supported on ARM has not been true for a while.
In fact, until recently, that was only supported for Thumb.  Besides that,
CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have
no effect on Thumb alignment.

llvm-svn: 83916
2009-10-12 22:49:05 +00:00
Bob Wilson 3250e7769f Change CreateNewWater method to return NewMBB by reference.
llvm-svn: 83905
2009-10-12 21:39:43 +00:00
Bob Wilson cc121aa750 Last week, ARMConstantIslandPass was failing to converge for the
MultiSource/Benchmarks/MiBench/automotive-susan test.  The failure has
since been masked by an unrelated change (just randomly), so I don't have
a testcase for this now.  Radar 7291928.

The situation where this happened is that a constant pool entry (CPE) was
placed at a lower address than the load that referenced it.  There were in
fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were
close together in the code.  The distance from the loads to the CPEs was
right at the limit of what they could handle, so that only one of the CPEs
could be placed within range.  On every iteration, the first CPE was found
to be out of range, causing a new CPE to be inserted.  The second CPE had
been in range but the newly inserted entry pushed it too far away.  Thus the
second CPE was also replaced by a new entry, which in turn pushed the first
CPE out of range.  Etc.

Judging from some comments in the code, the initial implementation of this
pass did not support CPEs placed _before_ their references.  In the case
where the CPE is placed at a higher address, the key to making the algorithm
terminate is that new CPEs are only inserted at the end of a group of adjacent
CPEs.  This is implemented by removing a basic block from the "WaterList"
once it has been used, and then adding the newly inserted CPE block to the
list so that the next insertion will come after it.  This avoids the ping-pong
effect where CPEs are repeatedly moved to the beginning of a group of
adjacent CPEs.  This does not work when going backwards, however, because the
entries at the end of an adjacent group of CPEs are closer than the CPEs
earlier in the group.

To make this pass terminate, we need to maintain a property that changes can
only happen in some sort of monotonic fashion.  The fix used here is to require
that the CPE for a particular constant pool load can only move to lower
addresses.  This is a very simple change to the code and should not cause
any significant degradation in the results.

llvm-svn: 83902
2009-10-12 21:23:15 +00:00
Bob Wilson e4adae267e Another minor clean-up.
llvm-svn: 83897
2009-10-12 20:45:53 +00:00
Bob Wilson 196bf32ab0 Remove redundant parameter.
llvm-svn: 83894
2009-10-12 20:37:23 +00:00
Bob Wilson 3a7326e705 Use early exit to reduce indentation.
llvm-svn: 83874
2009-10-12 19:04:03 +00:00
Bob Wilson 3af34312d4 Change to return a value by reference.
llvm-svn: 83873
2009-10-12 19:01:12 +00:00
Bob Wilson c7a3cf4066 Add a typedef for an iterator.
llvm-svn: 83872
2009-10-12 18:52:13 +00:00
Evan Cheng 6f012d83f2 ARM::tPOP and tPOP_RET each has an extra writeback operand now.
llvm-svn: 83214
2009-10-01 20:54:53 +00:00
Chris Lattner af29ea6d57 eliminate the last DOUTs from the targets.
llvm-svn: 79833
2009-08-23 06:49:22 +00:00
Chris Lattner a6f074fb3a remove various std::ostream version of printing methods from
MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813
2009-08-23 03:41:05 +00:00
Evan Cheng e41903b10d Also shrink immediate branches; also more assembler workarounds.
llvm-svn: 79014
2009-08-14 18:31:44 +00:00
Evan Cheng db73d68cbe Shrink ADR and LDR from constantpool late during constantpool island pass.
llvm-svn: 78970
2009-08-14 00:32:16 +00:00
Evan Cheng f59e9f4288 tPOP_RET now has predicate operands.
llvm-svn: 78898
2009-08-13 06:05:07 +00:00
Evan Cheng 81348021b1 Remove another Darwin assembler workaround.
llvm-svn: 78779
2009-08-12 02:07:19 +00:00
Evan Cheng cc9ca3500d Shrinkify Thumb2 load / store multiple instructions.
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
Jim Grosbach f24f9d9cb6 Whitespace cleanup. Remove trailing whitespace.
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
Evan Cheng 192d7c0752 Cosmetic changes.
llvm-svn: 78655
2009-08-11 07:36:14 +00:00
Evan Cheng 82ff022ed2 Error out, rather than infinite looping, if constant island pass can't converge.
llvm-svn: 78377
2009-08-07 07:35:21 +00:00
Evan Cheng 317bd7aab2 tBfar is bl, which clobbers LR.
llvm-svn: 78370
2009-08-07 05:45:07 +00:00
Evan Cheng e64f48ba8b Workaround a couple of Darwin assembler bugs.
llvm-svn: 77781
2009-08-01 06:13:52 +00:00
Evan Cheng f6d0fa3d33 - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.

llvm-svn: 77701
2009-07-31 18:28:05 +00:00
Evan Cheng e3493a91cc tbb / tbh instructions only branch forward, not backwards.
llvm-svn: 77522
2009-07-29 23:20:20 +00:00
Evan Cheng c6d70ae063 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
llvm-svn: 77422
2009-07-29 02:18:14 +00:00
Evan Cheng f3a1fce8ae Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
2009-07-25 00:33:29 +00:00
Evan Cheng c26c76ec1d Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.
llvm-svn: 76995
2009-07-24 19:31:03 +00:00
Evan Cheng 666c912ce3 Make sure thumb2 jumptable entries are aligned.
llvm-svn: 76986
2009-07-24 18:20:44 +00:00
Evan Cheng d2919a1773 Fix up ARM constant island pass for Thumb2.
Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890
2009-07-23 18:27:47 +00:00
Evan Cheng 87aaa194f9 Fixing cp island pass. Step 1: Determine whether the constant pool offset can be
negative on an individual bases rather than basing on whether it's in thumb
mode.

llvm-svn: 76698
2009-07-21 23:56:01 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin 56d0659726 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
2009-07-11 20:10:48 +00:00
David Goodwin 22c2fba978 Use common code for both ARM and Thumb-2 instruction and register info.
llvm-svn: 75067
2009-07-08 23:10:31 +00:00
Evan Cheng 7c9434399d 80 col violation.
llvm-svn: 74888
2009-07-07 01:16:41 +00:00
Bob Wilson deb35afd23 Add a new addressing mode for NEON load/store instructions.
llvm-svn: 74658
2009-07-01 23:16:05 +00:00
David Goodwin 28d6d87244 Improve Thumb-2 jump table support.
llvm-svn: 74549
2009-06-30 19:50:22 +00:00
David Goodwin 27303cde82 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
llvm-svn: 74543
2009-06-30 18:04:13 +00:00
Evan Cheng b23b50d54d Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
2009-06-29 07:51:04 +00:00
Bob Wilson ce8cfb41e8 Fix up a few minor typos in comments.
llvm-svn: 71563
2009-05-12 17:35:29 +00:00
Bob Wilson 2f4e56fd2e Fix 80-col violations and remove trailing whitespace. No functional changes.
llvm-svn: 71562
2009-05-12 17:09:30 +00:00
Duncan Sands af9eaa830a Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.

llvm-svn: 71349
2009-05-09 07:06:46 +00:00
Dale Johannesen 7647da67ea Remove refs to non-DebugLoc versions of BuildMI from ARM.
llvm-svn: 64429
2009-02-13 02:25:56 +00:00
Evan Cheng e4510972a6 Suppress a compile time warning.
llvm-svn: 63161
2009-01-28 00:53:34 +00:00
Duncan Sands dc020f9c3c Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.

llvm-svn: 62099
2009-01-12 20:38:59 +00:00
Evan Cheng 454ff53d58 Use ARMFunctionInfo to track number of constpool entries and jumptables.
llvm-svn: 58877
2008-11-08 00:51:41 +00:00
Dan Gohman 0d1e9a8e04 Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Dan Gohman 38453eebdc Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Dan Gohman a79db30d28 Tidy up several unbeseeming casts from pointer to intptr_t.
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
Dan Gohman 3b46030375 Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212
2008-07-07 23:14:23 +00:00
Nicolas Geoffray ae84bbdbed Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Chris Lattner 596875118c rename MachineInstr::setInstrDescriptor -> setDesc
llvm-svn: 45871
2008-01-11 18:10:50 +00:00
Chris Lattner 03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner a98c679de0 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
2008-01-07 01:56:04 +00:00
Chris Lattner a5bb370aa4 Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464
2007-12-30 23:10:15 +00:00
Chris Lattner 5c4637816e Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Duncan Sands 283207a71c Eliminate the remaining uses of getTypeSize. This
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688
2007-11-05 00:04:43 +00:00
Dale Johannesen 85ee72f7ba ARM: make branch folder remove unconditional branches
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782
2007-07-12 16:45:35 +00:00
Dale Johannesen e59411d056 Fix hang compiling TimberWolf (allow for islands
of size other than 4).

llvm-svn: 39743
2007-07-11 18:32:38 +00:00
Evan Cheng 94579dbd2e Didn't mean the last commit. Revert.
llvm-svn: 38515
2007-07-10 22:00:16 +00:00
Evan Cheng effa7467b6 Update.
llvm-svn: 38513
2007-07-10 21:49:47 +00:00
Evan Cheng 94f04c6fc9 Reflects the chanegs made to PredicateOperand.
llvm-svn: 37898
2007-07-05 07:18:20 +00:00
Evan Cheng c95f95b6da Fix comment.
llvm-svn: 37098
2007-05-16 05:14:06 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Devang Patel 8c78a0bff0 Drop 'const'
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
Devang Patel e95c6ad802 Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.

llvm-svn: 36652
2007-05-02 21:39:20 +00:00
Devang Patel 09f162ca6a Do not use typeinfo to identify pass in pass manager.
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
Dale Johannesen 4a00cf3fc4 Rewrite of Thumb constant islands handling (exact allowance for padding
around islands and jump tables).

llvm-svn: 36573
2007-04-29 19:19:30 +00:00
Evan Cheng 559c546453 Doh. ARM::LEApcrel is a single instruction MI.
llvm-svn: 36513
2007-04-27 18:27:13 +00:00
Evan Cheng d9990f061f Special handling of LEApcrel and tLEApcrel.
llvm-svn: 36504
2007-04-27 08:14:15 +00:00
Dale Johannesen fdfb757682 Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining
BBOffsets and BBSizes when adjusting conditional branches.

llvm-svn: 36372
2007-04-23 20:09:04 +00:00
Evan Cheng 3c68d4e8ba Remove unused constant pool entries.
llvm-svn: 35635
2007-04-03 23:39:48 +00:00
Dale Johannesen d13786dd82 fix off by 1 error in displacement computation
llvm-svn: 35602
2007-04-02 20:31:06 +00:00
Evan Cheng 6f059e3e0a - Track which callee-saved registers are spilled.
- Some code clean up.

llvm-svn: 34783
2007-03-01 08:26:31 +00:00
Dale Johannesen 962fa8eb9a Changes requested in review of last pass. Also pulled isThumb into a
member, instead of resetting in every function that uses it.

llvm-svn: 34764
2007-02-28 23:20:38 +00:00
Dale Johannesen 440995bd9a Add intelligence about where to break large blocks.
llvm-svn: 34755
2007-02-28 18:41:23 +00:00
Dale Johannesen c2f3d015e0 cosmetic changes from review of last patch. obvious
llvm-svn: 34598
2007-02-25 18:31:31 +00:00
Dale Johannesen e80e31eada remove crediting of Evan Cheng and me.
llvm-svn: 34568
2007-02-25 01:42:36 +00:00
Dale Johannesen 01ee5750f4 Removed WaterListOffset, inserted BBOffsets. Remove TODO item about this
from README.
When no water available, use end of block if in range.  (More to do here.)

llvm-svn: 34563
2007-02-25 00:47:03 +00:00
Dale Johannesen e18b13b213 rewrite of constant islands
llvm-svn: 34523
2007-02-23 05:02:36 +00:00
Evan Cheng 540f5e0d41 These vectors are frequently large. Use std::vector instead.
llvm-svn: 34109
2007-02-09 23:59:14 +00:00
Evan Cheng 8b7700f146 Add reference counting to constantpool entries. Delete the unused ones.
llvm-svn: 34105
2007-02-09 20:54:44 +00:00