d7518896ff
[X86][SSE] Fix domains for VZEXT_LOAD type instructions
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Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions.
Differential Revision: https://reviews.llvm.org/D27684
llvm-svn: 289825
2016-12-15 16:05:29 +00:00
41e31ff6bd
[X86][SSE] Regenerated the vec_set tests.
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Replaced lots of dodgy greps with actual codegen
llvm-svn: 265163
2016-04-01 17:40:25 +00:00
3f0fdbdfd1
Fix a typo in the mattr part of the run line.
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llvm-svn: 192174
2013-10-08 06:12:26 +00:00
3ede2f8a16
Explicitly disable AVX on a bunch of tests so they won't fail on AVX machines post r192171.
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llvm-svn: 192173
2013-10-08 06:06:57 +00:00
0828ab04bf
Attempt to fix -mtriple=i686-{cygwin|mingw|win32} regressions. Nakamura,
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if this doesn't work, please provide more details.
llvm-svn: 140107
2011-09-20 00:08:12 +00:00
646dd0f4d1
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
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This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
llvm-svn: 133524
2011-06-21 17:35:13 +00:00
c7df192279
Emit movq for 64-bit register to XMM register moves, but continue to accept
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movd when assembling.
llvm-svn: 133452
2011-06-20 18:33:26 +00:00
40503396da
Eliminate more uses of llvm-as and llvm-dis.
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llvm-svn: 81290
2009-09-08 23:54:48 +00:00
961339bbdb
Handle a few more cases of folding load i64 into xmm and zero top bits.
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Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.
llvm-svn: 50918
2008-05-09 21:53:03 +00:00
78af38c392
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
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llvm-svn: 50838
2008-05-08 00:57:18 +00:00
Simon Pilgrim