7c7bf1b432
Added a template for building target specific memory node in DAG.
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I added API for creation a target specific memory node in DAG. Today, all memory nodes are common for all targets and their constructors are located in SelectionDAG.cpp.
There are some cases in X86 where we need to create a special node - truncation-with-saturation store, float-to-half-store.
In the current patch I added truncation-with-saturation nodes and I'm using them for intrinsics. In the future I plan to implement DAG lowering for truncation-with-saturation pattern.
Differential Revision: https://reviews.llvm.org/D27899
llvm-svn: 290250
2016-12-21 10:43:36 +00:00
edab02b50b
[X86] Remove masking from 512-bit PSHUFB intrinsics in preparation for being able to constant fold it in InstCombineCalls like we do for 128/256-bit.
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llvm-svn: 289344
2016-12-10 23:09:43 +00:00
39c3c89cdc
MCStreamer: Use "cfi" for CFI related temp labels.
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Choosing a "cfi" name makes the intend a bit clearer in an assembly dump
and more importantly the assembly dumps are slightly more stable as the
numbers don't move around anymore when unrelated code calls
createTempSymbol() more or less often.
As they are temp labels the name doesn't influence the generated object
code.
Differential Revision: https://reviews.llvm.org/D27244
llvm-svn: 288290
2016-11-30 23:48:26 +00:00
02b5a1b50f
[AVX-512] Replace masked 16-bit element variable shift intrinsics with new unmasked versions and selects.
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The same thing was done to 32-bit and 64-bit element sizes previously.
This will allow us to support these shuffls in InstCombineCalls along with the other variable shift intrinsics.
llvm-svn: 287312
2016-11-18 05:04:44 +00:00
da6a63db1c
[AVX-512] Remove the remaining masked shift by immediate or by single value. Autoupgrade them to recently introduced unmasked versions and a select.
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After this I'll add the unmasked intrinsics to InstCombineCalls to finish making our handling of these types of shuffles consistent between AVX-512 and the legacy intrinsics.
llvm-svn: 286725
2016-11-12 18:04:46 +00:00
9d25c5e2fa
[AVX-512] Add unmasked version of shift by immediate and shift by single element in XMM.
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Summary:
This is the first step towards being able to add the avx512 shift by immediate intrinsics to InstCombineCalls where we aleady support the sse2 and avx2 intrinsics. We need to the unmasked versions so we can avoid having to teach InstCombineCalls that it would need to insert selects sometimes. Instead we'll just add the selects around the new instrinsics in the frontend.
This change should also enable the shift by i32 intrinsics to take a non-constant shift value just like the avx2 and sse intrinsics. This will enable us to fix PR30691 once we update clang.
Next I'll switch clang to use the new builtins. Then we'll come back to the backend and remove/autoupgrade the old intrinsics. Then I'll work on the same series for variable shifts.
Reviewers: RKSimon, zvi, delena
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26333
llvm-svn: 286711
2016-11-12 05:28:24 +00:00
b110e04851
[AVX-512] Remove masked pmovzx/pmovsx builtins and autoupgrade them to selects and native zext/sext.
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This mostly reuses earlier autoupgrade support for the sse and avx equivalents. Just needed to add the code to add the select.
llvm-svn: 286092
2016-11-07 02:12:57 +00:00
8ec5c7326d
[AVX-512] Remove masked pmin/pmax intrinsics and autoupgrade to native IR.
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Clang patch to replace 512-bit vector and 64-bit element versions with native IR will follow.
llvm-svn: 284955
2016-10-24 04:04:16 +00:00
f4151bea72
[AVX512] Add initial support for the Execution Domain fixing pass to change some EVEX instructions.
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llvm-svn: 276393
2016-07-22 05:00:52 +00:00
68f438a036
[X86][AVX512] Add support for PMOVZX masked shuffle comments
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llvm-svn: 274461
2016-07-03 13:33:28 +00:00
597aa42fec
[AVX512] Remove masked unpack intrinsics and autoupgrade to vectorshuffle and selects.
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llvm-svn: 273543
2016-06-23 07:37:33 +00:00
0a0fb0fda1
[AVX512] Remove the masked vpcmpeq/vcmpgt intrinsics and autoupgrade them to native icmps.
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llvm-svn: 273240
2016-06-21 03:53:24 +00:00
e59165ca63
[AVX512] [AVX512/AVX][Intrinsics] Fix Variable Bit Shift Right Arithmetic intrinsic lowering.
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Differential Revision: http://reviews.llvm.org/D20897
llvm-svn: 273138
2016-06-20 07:05:43 +00:00
13cf7cac07
[AVX512] Remove maksed pshufd, pshuflw, and phufhw intrinsics and autoupgrade them to selects and shufflevector.
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llvm-svn: 272527
2016-06-13 02:36:48 +00:00
89c1761474
[AVX512] Fix shuffle comment printing to handle the masked versions of some shuffles. Previously we were printing the mask operands as the register names.
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llvm-svn: 272367
2016-06-10 04:48:05 +00:00
f718682eb9
[X86][AVX512] Dropped avx512 VPSLLDQ/VPSRLDQ intrinsics
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Auto-upgrade to generic shuffles like sse/avx2 implementations now that we can lower to VPSLLDQ/VPSRLDQ
llvm-svn: 272308
2016-06-09 21:09:03 +00:00
f635367e2b
[AVX512] Remove masked_move/blendm intrinsic from back-end.
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This is complement patch to D21060.
Differential Revision: http://reviews.llvm.org/D21174
llvm-svn: 272257
2016-06-09 11:46:55 +00:00
6f7288dc44
[AVX512] Fix shuffle decode printing for several instructions with write masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix.
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llvm-svn: 272252
2016-06-09 07:49:08 +00:00
33350cc406
[AVX512] Remove masked palignr intrinsics and auto-upgrade them to native IR of vector shuffle and select.
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llvm-svn: 271872
2016-06-06 06:12:54 +00:00
ccad6d57c1
[AVX512] Update tests to show shuffle decoding for vpshuflw/vpshufhw.
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llvm-svn: 271869
2016-06-06 05:39:07 +00:00
f10fbfa738
[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead.
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The intrinsics will be autoupgraded to the same generic masked loads.
llvm-svn: 271478
2016-06-02 04:19:36 +00:00
4f2d5a68d3
Revert r271362 "[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead."
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Looks like something isn't quite right still. Also forgot to move the test cases to an autoupgrade test.
llvm-svn: 271363
2016-06-01 05:57:55 +00:00
dacd9d2bac
[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead.
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The intrinsics will be autoupgraded to the same generic masked loads.
llvm-svn: 271362
2016-06-01 05:35:16 +00:00
50f85c22c5
[AVX512] Remove masked store intrinsics. Clang now emits generic masked store intrinsics instead.
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The intrinsics will be autoupgraded to the same generic masked stores.
llvm-svn: 271245
2016-05-31 01:50:02 +00:00
23c2090606
[llvm][AVX512][intrinsics] Fix vperm{b|w|d|q|ps|pd} intrinsics. Index is second argument to buildin function but it is first instruction operand.
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Differential Revision: http://reviews.llvm.org/D20515
llvm-svn: 270548
2016-05-24 11:06:22 +00:00
87d05b9852
[X86][AVX512] Regenerate intrinsics test
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llvm-svn: 269193
2016-05-11 15:13:29 +00:00
e0a6fc3bcc
[X86] Fix PR23155 by turning on X86FixupBWInsts by default.
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Differential Revision: http://reviews.llvm.org/D18866
llvm-svn: 265830
2016-04-08 18:58:29 +00:00
c4d054fa4a
[LLVM][AVX512] PSRLWI Chnage imm8 to int
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Differential Revision: http://reviews.llvm.org/D17753
llvm-svn: 262592
2016-03-03 08:54:05 +00:00
927fdaee88
[LLVM][AVX512]PSRAWI Change imm8 to int.
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Differential Revision: http://reviews.llvm.org/D17705
llvm-svn: 262480
2016-03-02 12:05:07 +00:00
96836fc81c
[AVX512][PSLLW ][PSLLV] Change imm8 to int
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Differential Revision: http://reviews.llvm.org/D17684
llvm-svn: 262176
2016-02-28 07:32:10 +00:00
a1f2d27da2
[LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int
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Differential Revision: http://reviews.llvm.org/D17538
llvm-svn: 261725
2016-02-24 08:39:05 +00:00
0aeda37464
AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation.
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Differential Revision: http://reviews.llvm.org/D16813
llvm-svn: 260024
2016-02-07 08:30:50 +00:00
1bd7f993fc
[AVX512] Adding PTESTNMB/D/W/Q instruction
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Differential Revision: http://reviews.llvm.org/D16520
llvm-svn: 258688
2016-01-25 14:43:23 +00:00
19670d479a
[AVX512] Adding PTESTMB/W/D/Q instruction
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Differential Revision: http://reviews.llvm.org/D16519
llvm-svn: 258686
2016-01-25 13:27:32 +00:00
29cde35b43
Added Skylake client to X86 targets and features
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Changes in X86.td:
I set features of Intel processors in incremental form: IVB = SNB + X HSW = IVB + X ..
I added Skylake client processor and defined it's features
FeatureADX was missing on KNL
Added some new features to appropriate processors SMAP, IFMA, PREFETCHWT1, VMFUNC and others
Differential Revision: http://reviews.llvm.org/D16357
llvm-svn: 258659
2016-01-24 10:41:28 +00:00
1e5bafbc82
AVX512: VMOVDQU8/16/32/64 (load) intrinsic implementation.
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Differential Revision: http://reviews.llvm.org/D16137
llvm-svn: 258657
2016-01-24 08:04:33 +00:00
7a000f5bb2
AVX512: Masked move intrinsic implementation.
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Implemented intrinsic for the follow instructions (reg move) : VMOVDQU8/16, VMOVDQA32/64, VMOVAPS/PD.
Differential Revision: http://reviews.llvm.org/D16316
llvm-svn: 258398
2016-01-21 14:18:11 +00:00
239fda676c
AVX512: Masked store intrinsic implementation.
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Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD.
Differential Revision: http://reviews.llvm.org/D16271
llvm-svn: 258047
2016-01-18 13:52:57 +00:00
ac1b238b0a
[AVX512] Adding VPERMW/D/Q VPERMPS/D Intrinsics
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Differential Revision: http://reviews.llvm.org/D16189
llvm-svn: 258008
2016-01-17 11:33:29 +00:00
0e31b22487
[AVX512] Adding PMOVSXBD/W/Q , PMOVZSDQ and PMOVZSWD/Q Intrinsics .
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Differential Revision: http://reviews.llvm.org/D16111
llvm-svn: 257604
2016-01-13 14:59:19 +00:00
43cea85db9
[AVX512] Adding PMOVZXBD/W/Q , PMOVZXDQ and PMOVZXWD/Q Intrinsics
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Differential Revision:http://reviews.llvm.org/D16071
llvm-svn: 257601
2016-01-13 14:25:21 +00:00
5b1cad87aa
[avx512] Fix test avx512bw-intrinsics.ll
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Change the CHECK lablel into AVX512BW
And fix declare lable of llvm.x86.avx512.mask.psrav32_hi
llvm-svn: 257071
2016-01-07 16:25:42 +00:00
3aca221b31
[AVX512] add PSLLW and PSLLV Intrinsic
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Differential Revision: http://reviews.llvm.org/D15889
llvm-svn: 257070
2016-01-07 16:02:51 +00:00
354152d590
[AVX512] add PSRAV Intrinsic
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Differential Revision: http://reviews.llvm.org/D15856
llvm-svn: 257063
2016-01-07 14:42:20 +00:00
a6df006b50
[AVX512] add PSHUFHW and PSHUFLW Intrinsic
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Differential Revision: http://reviews.llvm.org/D15925
llvm-svn: 257056
2016-01-07 12:35:43 +00:00
000fca44a8
[AVX512] add PSRAW Intrinsic
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Differential Revision: http://reviews.llvm.org/D15850
llvm-svn: 256751
2016-01-04 12:50:36 +00:00
068bc2f219
[AVX512] add PSRLV Intrinsic
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Differential Revision: http://reviews.llvm.org/D15838
llvm-svn: 256747
2016-01-04 11:39:06 +00:00
80821ee77c
[AVX512] add PSRLW Intrinsic
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Differential Revision: http://reviews.llvm.org/D15751
llvm-svn: 256558
2015-12-29 13:04:35 +00:00
756c289dd8
AVX512: Change VPMOVB2M DAG lowering , use CVT2MASK node instead TRUNCATE.
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Fix TRUNCATE lowering vector to vector i1, use LSB and not MSB.
Implement VPMOVB/W/D/Q2M intrinsic.
Differential Revision: http://reviews.llvm.org/D15675
llvm-svn: 256470
2015-12-27 13:56:16 +00:00
268f6f53c5
AVX512: VPMOVM2B/W/D/Q intrinsic implementation.
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Differential Revision: http://reviews.llvm.org//D15747
llvm-svn: 256364
2015-12-24 07:11:53 +00:00
Elena Demikhovsky