llvm-project

Commit Graph

Author	SHA1	Message	Date
Oliver Stannard	e093bad472	[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779	2017-10-03 10:26:11 +00:00
Tim Northover	41d2049180	ARM: tweak test to pass on all platforms A TableGen indeterminacy means that the reason for the failure can vary, and Windows gets the other option. llvm-svn: 193394	2013-10-25 07:34:56 +00:00
Tim Northover	5620faf771	ARM: Mark double-precision instructions as such This prevents us from silently accepting invalid instructions on (for example) Cortex-M4 with just single-precision VFP support. No tests for the extra Pat Requires because they're essentially assertions: the affected code should have been lowered to libcalls before ISel. rdar://problem/15302004 llvm-svn: 193354	2013-10-24 15:49:39 +00:00

Author

SHA1

Message

Date

Oliver Stannard

e093bad472

[ARM] Use new assembler diags for ARM

This converts the ARM AsmParser to use the new assembly matcher error
reporting mechanism, which allows errors to be reported for multiple
instruction encodings when it is ambiguous which one the user intended
to use.

By itself this doesn't improve many error messages, because we don't have
diagnostic text for most operand types, but as we add that then this will allow
more of those diagnostic strings to be used when they are relevant.

Differential revision: https://reviews.llvm.org/D31530

llvm-svn: 314779

2017-10-03 10:26:11 +00:00

Tim Northover

41d2049180

ARM: tweak test to pass on all platforms

A TableGen indeterminacy means that the reason for the failure can
vary, and Windows gets the other option.

llvm-svn: 193394

2013-10-25 07:34:56 +00:00

Tim Northover

5620faf771

ARM: Mark double-precision instructions as such

This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.

No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.

rdar://problem/15302004

llvm-svn: 193354

2013-10-24 15:49:39 +00:00

3 Commits