Commit Graph

20 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih 25528d6de7 [CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665
2017-12-04 17:18:51 +00:00
Rafael Espindola 1e6b49e144 Add back a CHECK line.
I accidentally removed it in r307730.

Thanks to Martin Storsjö for noticing!

llvm-svn: 307801
2017-07-12 16:14:00 +00:00
Rafael Espindola 1beb702ba2 Fully fix the movw/movt addend.
The issue is not if the value is pcrel. It is whether we have a
relocation or not.

If we have a relocation, the static linker will select the upper
bits. If we don't have a relocation, we have to do it.

llvm-svn: 307730
2017-07-11 23:18:25 +00:00
Martin Storsjo 0e83e85f63 [ARM, ELF] Don't shift movt relocation offsets
For ELF, a movw+movt pair is handled as two separate relocations.
If an offset should be applied to the symbol address, this offset is
stored as an immediate in the instruction (as opposed to stored as an
offset in the relocation itself).

Even though the actual value stored in the movt immediate after linking
is the top half of the value, we need to store the unshifted offset
prior to linking. When the relocation is made during linking, the offset
gets added to the target symbol value, and the upper half of the value
is stored in the instruction.

This makes sure that movw+movt with offset symbols get properly
handled, in case the offset addition in the lower half should be
carried over to the upper half.

This makes the output from the additions to the test case match
the output from GNU binutils.

For COFF and MachO, the movw/movt relocations are handled as a pair,
and the overflow from the lower half gets carried over to the movt,
so they should keep the shifted offset just as before.

Differential Revision: https://reviews.llvm.org/D35242

llvm-svn: 307713
2017-07-11 21:07:10 +00:00
Rafael Espindola f9df429068 Also test thumb.
llvm-svn: 305976
2017-06-22 00:44:05 +00:00
Rafael Espindola 2c8e3ed00f Simplify test.
llvm-svn: 305881
2017-06-21 06:42:56 +00:00
Rafael Espindola 54a381463e No need to check the raw relocation bytes if checking the parsed dump.
llvm-svn: 239042
2015-06-04 15:21:17 +00:00
Rafael Espindola bb35ebd189 Don't special case undefined symbol when deciding the symbol order.
ELF has no restrictions on where undefined symbols go relative to other defined
symbols. In fact, gas just sorts them together. Do the same.

This was there since r111174 probably just because the MachO writer has it.

llvm-svn: 238513
2015-05-28 21:59:34 +00:00
Rafael Espindola cad91323dc Don't constrain the section order in tests that don't depend on it.
llvm-svn: 236102
2015-04-29 13:55:07 +00:00
Rafael Espindola 10f3de6889 Update tests to not be as dependent on section numbers.
Many of these predate llvm-readobj. With elf-dump we had to match
a relocation to symbol number and symbol number to symbol name or
section number.

llvm-svn: 235015
2015-04-15 15:59:37 +00:00
Rafael Espindola 7230f80e3b Write the section header in the end.
One could make the argument for writing it immediately after the ELF header,
but writing it in the middle of the sections like we were doing just makes
it harder for no reason.

llvm-svn: 234400
2015-04-08 11:41:24 +00:00
Rafael Espindola 4f60a38f18 Change how we iterate over relocations on ELF.
For COFF and MachO, sections semantically have relocations that apply to them.
That is not the case on ELF.

In relocatable objects (.o), a section with relocations in ELF has offsets to
another section where the relocations should be applied.

In dynamic objects and executables, relocations don't have an offset, they have
a virtual address. The section sh_info may or may not point to another section,
but that is not actually used for resolving the relocations.

This patch exposes that in the ObjectFile API. It has the following advantages:

* Most (all?) clients can handle this more efficiently. They will normally walk
all relocations, so doing an effort to iterate in a particular order doesn't
save time.

* llvm-readobj now prints relocations in the same way the native readelf does.

* probably most important, relocations that don't point to any section are now
visible. This is the case of relocations in the rela.dyn section. See the
updated relocation-executable.test for example.

llvm-svn: 182908
2013-05-30 03:05:14 +00:00
Nico Rieck ba848e3bca Replace coff-/elf-dump with llvm-readobj
llvm-svn: 179361
2013-04-12 04:06:46 +00:00
Rafael Espindola 260af5cef6 Print r_type with the correct number of bits.
llvm-svn: 136872
2011-08-04 14:39:30 +00:00
Rafael Espindola 65c559c5fb Change anther counter to decimal.
llvm-svn: 136870
2011-08-04 14:01:03 +00:00
Jason W Kim d0c937d4b2 This fixes one divergence between LLVM and binutils for ARM in the
text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

llvm-svn: 131674
2011-05-19 20:55:25 +00:00
Evan Cheng d4a5c05c97 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.

llvm-svn: 123424
2011-01-14 02:38:49 +00:00
Evan Cheng 965b3c7323 Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369
2011-01-13 07:58:56 +00:00
Jason W Kim 9c5b65d289 1. Support ELF pcrel relocations for movw/movt:
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294
2011-01-12 00:19:25 +00:00
Jason W Kim 1f7bc0707d Workaround for bug 8721.
.s Test added.

llvm-svn: 123292
2011-01-11 23:53:41 +00:00