d29f24acfb
[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
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Differential Revision: https://reviews.llvm.org/D40098
llvm-svn: 320083
2017-12-07 20:34:25 +00:00
a41351e37c
AMDGPU: Move hazard avoidance out of waitcnt pass.
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This is mostly moving VMEM clause breaking into
the hazard recognizer. Also move another hazard
currently handled in the waitcnt pass.
Also stops breaking clauses unless xnack is enabled.
llvm-svn: 318557
2017-11-17 21:35:32 +00:00
03c67d1eb2
AMDGPU: Fix breaking SMEM clauses
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This was completely ignoring subregisters,
so was not very useful. Also only break them
if xnack is actually enabled.
llvm-svn: 318505
2017-11-17 04:18:24 +00:00
59ece95f6c
AMDGPU: Fix broken condition in hazard recognizer
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Fixes bug 32248.
llvm-svn: 298125
2017-03-17 21:36:28 +00:00
e823d92f7f
AMDGPU: Merge initial gfx9 support
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llvm-svn: 295554
2017-02-18 18:29:53 +00:00
aea899e2a0
AMDGPU/SI: Handle hazard with s_rfe_b64
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Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25638
llvm-svn: 285368
2016-10-27 23:50:21 +00:00
04051b5fad
AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}lane
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Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25637
llvm-svn: 285367
2016-10-27 23:42:29 +00:00
b133fbb9a4
AMDGPU/SI: Handle hazard with > 8 byte VMEM stores
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Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25577
llvm-svn: 285359
2016-10-27 23:05:31 +00:00
30d30824b4
AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer
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Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25528
llvm-svn: 285338
2016-10-27 20:39:09 +00:00
961811c906
AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer
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Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25526
llvm-svn: 284298
2016-10-15 00:58:14 +00:00
5ab6154dc3
AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizer
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Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25250
llvm-svn: 283622
2016-10-07 23:42:48 +00:00
43e92fe306
AMDGPU: Cleanup subtarget handling.
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Split AMDGPUSubtarget into amdgcn/r600 specific subclasses.
This removes most of the static_casting of the basic codegen
classes everywhere, and tries to restrict the features
visible on the wrong target.
llvm-svn: 273652
2016-06-24 06:30:11 +00:00
d3f4c05aea
Move instances of std::function.
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Or replace with llvm::function_ref if it's never stored. NFC intended.
llvm-svn: 272513
2016-06-12 16:13:55 +00:00
1f520e5c98
AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses
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Summary:
Add support for detecting hazards in SMEM soft clauses, so that we only
break the clauses when necessary, either by adding s_nop or re-ordering
other alu instructions.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18870
llvm-svn: 268260
2016-05-02 17:39:06 +00:00
a27007eb4f
AMDGPU/SI: Use hazard recognizer to detect DPP hazards
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Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18603
llvm-svn: 268247
2016-05-02 16:23:09 +00:00
cb6ba62d6f
AMDGPU/SI: Enable the post-ra scheduler
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Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.
Reviewers: arsenm
Subscribers: qcolombet, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18602
llvm-svn: 268143
2016-04-30 00:23:06 +00:00
Mark Searles