0ba7b04f5f
AVX512BW: Fix SRA v64i8 lowering. Use PCMPGTM (cmp result in k register) for 512bit vector because PCMPGT supported only for 128/256bit.
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Differential Revision: http://reviews.llvm.org/D18204
llvm-svn: 263624
2016-03-16 08:48:26 +00:00
7b46b4e798
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts.
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Differential Revision: http://reviews.llvm.org/D15713
llvm-svn: 256324
2015-12-23 08:06:50 +00:00
7c905063c5
Make utils/update_llc_test_checks.py note that the assertions are
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autogenerated.
Also update existing test cases which appear to be generated by it and
weren't modified (other than addition of the header) by rerunning it.
llvm-svn: 253917
2015-11-23 21:33:58 +00:00
b38c09d7ff
[X86][AVX512] Added 512-bit vector shift tests.
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Only works for avx512f (dq) targets so far - need to add avx512bw tests once char/short shifts are supported.
llvm-svn: 246943
2015-09-06 13:36:32 +00:00
Igor Breger