Commit Graph

1598 Commits

Author SHA1 Message Date
Tom Stellard ae6c06e5de R600/SI: Make sample intrinsic address parameter type overloaded.
Handle vectors of 1 to 16 integers.

Change the intrinsic names to prevent the wrong one from being selected at
runtime due to the overloading.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174633
2013-02-07 17:02:13 +00:00
Tom Stellard 538ceeb6e0 R600/SI: Add basic support for more integer vector types.
v1i32, v2i32, v8i32 and v16i32.

Only add VGPR register classes for integer vector types, to avoid attempts
copying from VGPR to SGPR registers, which is not possible.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174632
2013-02-07 17:02:09 +00:00
Michel Danzer 349cabed2f R600/SI: Add pattern for flog2
22 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174615
2013-02-07 14:55:16 +00:00
Tom Stellard 9355b22180 R600: Consolidate sub register indices.
Use sub0-15 everywhere.

Patch by: Michel Dänzerr

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 174610
2013-02-07 14:02:37 +00:00
Tom Stellard e06163a9a6 R600: Add support for SET*_DX10 instructions
These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

llvm-svn: 174609
2013-02-07 14:02:35 +00:00
Tom Stellard b40ada9b85 R600: Fix assembly name for SETGT_INT
llvm-svn: 174607
2013-02-07 14:02:27 +00:00
Tom Stellard f3b2a1e8b3 R600: Support for indirect addressing v4
Only implemented for R600 so far.  SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.

At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.

v2:
  - Add support for i8 zext load from stack.
  - Coding style fixes

v3:
  - Don't reserve registers for indirect addressing when it isn't
    being used.
  - Fix bug caused by LLVM limiting the number of SubRegIndex
    declarations.

v4:
  - Fix 64-bit defines

llvm-svn: 174525
2013-02-06 17:32:29 +00:00
Jakob Stoklund Olesen fdc37670f6 Don't use MRI liveouts in R600.
Something very strange is going on with the output registers in this
target. Its ISelLowering code is inserting dangling CopyToReg nodes,
hoping that those physregs won't get clobbered before the RETURN.

This patch adds the output registers as implicit uses on RETURN
instructions in the custom emission pass. I'd much prefer to have those
CopyToReg nodes glued to the RETURNs, but I don't see how.

llvm-svn: 174400
2013-02-05 17:53:52 +00:00
Tom Stellard df063e617f R600: Fold remaining CONST_COPY after expand pseudo inst
Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174395
2013-02-05 17:09:16 +00:00
Tom Stellard 41afe6a6fe R600: improve inputs/interpolation handling
Use one intrinsic for all sorts of interpolation.
Use two separate unexpanded instructions to represent INTERP_XY and _ZW -
this will allow to eliminate one part if it's not used.
Track liveness of special interpolation regs instead of reserving them -
this will allow to reuse those regs, lowering reg pressure.

Patch By: Vadim Girlin

v2[Vincent Lejeune]: Rebased against current llvm master

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174394
2013-02-05 17:09:14 +00:00
Tom Stellard 2e5e7a5bef R600: Emit function name in the AsmPrinter
Emitting the function name allows us to check for it in the FileCheck
tests so we can make sure FileCheck is checking the output of the
correct function.

llvm-svn: 174392
2013-02-05 17:09:11 +00:00
Tom Stellard 836cdd97fe R600/SI: Add patterns for fcos and fsin.
Fixes 37 piglit tests and allows e.g. FlightGear to run with radeonsi.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174391
2013-02-05 17:09:10 +00:00
NAKAMURA Takumi e1137a2058 Update AMDGPURegisterInfo::eliminateFrameIndex() corresponding to r174083.
llvm-svn: 174106
2013-01-31 22:55:51 +00:00
Tom Stellard 4926921bd4 R600: Fold clamp, neg, abs
Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174099
2013-01-31 22:11:54 +00:00
Tom Stellard dd04c83a4d R600: Consider bitcast when folding const_address node.
Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174098
2013-01-31 22:11:53 +00:00
Tom Stellard af1bce7d1d R600: Make store_dummy intrinsic more general by passing export type
Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174097
2013-01-31 22:11:46 +00:00
NAKAMURA Takumi 978b5a0e02 R600/AMDILPeepholeOptimizer.cpp: Tweak std::make_pair to satisfy C++11.
llvm-svn: 173807
2013-01-29 16:31:56 +00:00
Tom Stellard 6f1b8657f9 R600: Add a llvm.R600.store.swizzle intrinsics
This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its
name. It is used to store vs/fs outputs

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 173297
2013-01-23 21:39:49 +00:00
Tom Stellard d8ac91d436 R600: Simplify stream outputs intrinsic
Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 173296
2013-01-23 21:39:47 +00:00
Tom Stellard 365366f9ef R600: rework handling of the constants
Remove Cxxx registers, add new special register - "ALU_CONST" and new
operand for each alu src - "sel". ALU_CONST is used to designate that the
new operand contains the value to override src.sel, src.kc_bank, src.chan
for constants in the driver.

Patch by: Vadim Girlin

Vincent Lejeune:
  - Use pointers for constants
  - Fold CONST_ADDRESS when possible

Tom Stellard:
  - Give CONSTANT_BUFFER_0 its own address space
  - Use integer types for constant loads

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 173222
2013-01-23 02:09:06 +00:00
Tom Stellard ff62c35da0 R600: Add a CONST_ADDRESS node to model constant buf read
Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 173221
2013-01-23 02:09:03 +00:00
Tom Stellard ab28e9a30a R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen def
Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 173220
2013-01-23 02:09:01 +00:00
Tom Stellard c9b903138d R600/SI: Use unnormalized coordinates for sampling with the RECT target.
Patch by: Michel Dänzer

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 173053
2013-01-21 15:40:48 +00:00
Tom Stellard 14421a793f R600/SI: Take target parameter for sample intrinsics.
Patch by: Michel Dänzer

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 173052
2013-01-21 15:40:47 +00:00
Tom Stellard 74dda0da31 R600/SI: Derive all sample intrinsics from a single class.
Patch by: Michel Dänzer

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 173051
2013-01-21 15:40:46 +00:00
NAKAMURA Takumi c96fb1bd36 R600/SILowerControlFlow.cpp: Fix a warning. [-Wunused-variable]
llvm-svn: 173040
2013-01-21 14:06:48 +00:00
Tom Stellard c4cabef782 R600: Proper insert S_WAITCNT instructions
Some instructions like memory reads/writes are executed
asynchronously, so we need to insert S_WAITCNT instructions
to block before accessing their results. Previously we have
just inserted S_WAITCNT instructions after each async
instruction, this patch fixes this and adds a prober
insertion pass.

Patch by: Christian König

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 172846
2013-01-18 21:15:53 +00:00
Tom Stellard be8ebeebf7 R600: Optimize and cleanup KILL on SI
We shouldn't insert KILL optimization if we don't have a
kill instruction at all.

Patch by: Christian König

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 172845
2013-01-18 21:15:50 +00:00
Dmitri Gribenko 226fea5bd6 Remove redundant 'llvm::' qualifications
llvm-svn: 172358
2013-01-13 16:01:15 +00:00
Eli Bendersky 4d9ada036c Renamed MCInstFragment to MCRelaxableFragment and added some comments.
No change in functionality.

llvm-svn: 171822
2013-01-08 00:22:56 +00:00
NAKAMURA Takumi 458a8277cc R600/SIISelLowering.cpp: Suppress a warning. [-Wunused-variable]
llvm-svn: 171728
2013-01-07 11:14:44 +00:00
Chandler Carruth 9fb823bbd4 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Chandler Carruth be81023d74 Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.

Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.

llvm-svn: 171362
2013-01-02 10:22:59 +00:00
Tom Stellard 09ef8425e9 R600: Coding style - remove empty spaces from the beginning of functions
No functionality change.

llvm-svn: 170923
2012-12-21 20:12:02 +00:00
Tom Stellard 41398026e7 R600: Fix MAX_UINT definition
Patch by: Vadim Girlin

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 170922
2012-12-21 20:12:01 +00:00
Tom Stellard 4fa7ac29f1 R600: Add SHADOWCUBE to TEX_SHADOW pattern
Patch by: Vadim Girlin

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 170921
2012-12-21 20:11:59 +00:00
Tom Stellard a8b0351720 R600: Expand vec4 INT <-> FP conversions
llvm-svn: 170901
2012-12-21 16:33:24 +00:00
NAKAMURA Takumi 2a0b40f584 Target/R600: Update MIB according to r170588.
llvm-svn: 170620
2012-12-20 00:22:11 +00:00
Tom Stellard 1c315d5411 R600: Remove unecessary VREG alignment.
Unlike SGPRs VGPRs doesn't need to be aligned.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170593
2012-12-19 22:10:34 +00:00
Tom Stellard e7b907d85c R600: control flow optimization
Branch if we have enough instructions so that it makes sense.
Also remove branches if they don't make sense.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170592
2012-12-19 22:10:33 +00:00
Tom Stellard f8794354b2 R600: New control flow for SI v2
This patch replaces the control flow handling with a new
pass which structurize the graph before transforming it to
machine instruction. This has a couple of different advantages
and currently fixes 20 piglit tests without a single regression.

It is now a general purpose transformation that could be not
only be used for SI/R6xx, but also for other hardware
implementations that use a form of structurized control flow.

v2: further cleanup, fixes and documentation

Patch by: Christian König

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 170591
2012-12-19 22:10:31 +00:00
Tom Stellard 5a6879466a R600: enable S_*N2_* instructions
They seem to work fine.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170343
2012-12-17 15:14:56 +00:00
Tom Stellard 9e90b5895d R600: BB operand support for SI
Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170342
2012-12-17 15:14:54 +00:00
Tom Stellard 16a17c6d3e R600: remove nonsense setPrefLoopAlignment
The Align parameter is a power of two, so 16 results in 64K
alignment. Additional to that even 16 byte alignment doesn't
make any sense, so just remove it.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170341
2012-12-17 15:14:53 +00:00
Tom Stellard 6975d35979 Fix warnings with -DNDEBUG
Patch by: NAKAMURA Takumi

llvm-svn: 170142
2012-12-13 19:38:52 +00:00
Jakob Stoklund Olesen 436eea9833 Avoid setIsInsideBundle in Target/R600.
This function is going to be removed.

llvm-svn: 170064
2012-12-13 00:59:38 +00:00
NAKAMURA Takumi 85292a1338 [CMake] Fixup R600.
llvm-svn: 169962
2012-12-12 03:34:26 +00:00
Tom Stellard 75aadc2813 Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
2012-12-11 21:25:42 +00:00