Commit Graph

1598 Commits

Author SHA1 Message Date
Tom Stellard b14ead55f4 R600/SI: Remove stray debug statements
llvm-svn: 227462
2015-01-29 16:55:28 +00:00
Tom Stellard 83f0bcef7a R600/SI: Define a schedule model and enable the generic machine scheduler
The schedule model is not complete yet, and could be improved.

llvm-svn: 227461
2015-01-29 16:55:25 +00:00
Tom Stellard 40ce8af4a5 R600: Move DataLayout to AMDGPUTargetMachine
This is a follow up to r227113.

It is now required to use the amdgcn target for SI and newer GPUs.

llvm-svn: 227316
2015-01-28 16:04:26 +00:00
Tom Stellard eba5648ad2 R600: Use a Southern Islands GPU as the default for the amdgcn target
llvm-svn: 227314
2015-01-28 15:38:42 +00:00
Marek Olsak 794ff8392e R600/SI: Fix MIN3/MAX3 on VI, define MED3
llvm-svn: 227213
2015-01-27 17:25:15 +00:00
Marek Olsak 367447c255 R600/SI: Don't set patterns for chip-specific instructions while having pseudos
Only pseudos have patterns on them.

Also don't set the asm string for VINTRP_Pseudo. All pseudos should have empty
asm.

This matches what all other multiclasses do.

llvm-svn: 227212
2015-01-27 17:25:11 +00:00
Marek Olsak 0c1f8812f5 R600/SI: Add VI versions of LDS atomics
Each class is split into two: one adds let statements around non-pseudos,
and the other one specifies the parameters.

llvm-svn: 227211
2015-01-27 17:25:07 +00:00
Marek Olsak 19d9e1f459 R600/SI: Add VI versions of MUBUF atomics
llvm-svn: 227210
2015-01-27 17:25:02 +00:00
Marek Olsak ee98b1177c R600/SI: Add VI versions of MUBUF loads and stores
This enables a lot of existing patterns for VI.

llvm-svn: 227209
2015-01-27 17:24:58 +00:00
Marek Olsak 7ef6db49ac R600/SI: Add pseudos for MUBUF loads and stores
This defines the SI versions only, so it shouldn't change anything.

There are no changes other than using the new multiclasses, adding missing
mayLoad/mayStore, and formatting fixes.

llvm-svn: 227208
2015-01-27 17:24:54 +00:00
Eric Christopher 8b7706517c Move DataLayout back to the TargetMachine from TargetSubtargetInfo
derived classes.

Since global data alignment, layout, and mangling is often based on the
DataLayout, move it to the TargetMachine. This ensures that global
data is going to be layed out and mangled consistently if the subtarget
changes on a per function basis. Prior to this all targets(*) have
had subtarget dependent code moved out and onto the TargetMachine.

*One target hasn't been migrated as part of this change: R600. The
R600 port has, as a subtarget feature, the size of pointers and
this affects global data layout. I've currently hacked in a FIXME
to enable progress, but the port needs to be updated to either pass
the 64-bitness to the TargetMachine, or fix the DataLayout to
avoid subtarget dependent features.

llvm-svn: 227113
2015-01-26 19:03:15 +00:00
Tom Stellard edd188c459 R600/SI: Emit .hsa.version section for amdhsa OS
llvm-svn: 226970
2015-01-23 23:59:08 +00:00
Tom Stellard 20f6c0732f R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()
We used to do this promotion during DAG legalization, but this
caused an infinite loop in ExpandUnalignedLoad() because it assumed
that i64 loads were legal if i64 was a legal type.

It also seems better to report i64 loads as legal, since they actually
are and we were just promoting them to simplify our tablegen files.

llvm-svn: 226945
2015-01-23 22:05:45 +00:00
Jan Vesely 5f715d36a7 R600: Try to use lower types for 64bit division if possible
v2: add and enable tests for SI

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>
llvm-svn: 226881
2015-01-22 23:42:43 +00:00
Jan Vesely f7987ca5a7 R600: Simplify LowerUDIVREM
optimizations can handle removing the Hi part operations.
The generated code is identical for R600, ~10% icount reduction for SI

v2: rebase

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>
llvm-svn: 226879
2015-01-22 23:42:39 +00:00
Matt Arsenault b00554886f R600/SI: Custom lower fround
This fixes it for SI. It also removes the pattern
used previously for Evergreen for f32. I'm not sure
if the the new R600 output is better or not, but it uses
1 fewer instructions if BFI is available.

llvm-svn: 226682
2015-01-21 18:18:25 +00:00
Tom Stellard e99fb65d87 R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
This is disabled by default, but can be enabled with the subtarget
feature: 'vgpr-spilling'

llvm-svn: 226597
2015-01-20 19:33:04 +00:00
Tom Stellard 021053f500 R600/SI: Fix simple-loop.ll test
llvm-svn: 226596
2015-01-20 19:33:02 +00:00
Tom Stellard 3a70d07f51 R600/SI: Remove stray debugging code from r226586
llvm-svn: 226591
2015-01-20 19:24:31 +00:00
Tom Stellard 95292bbfcd R600/SI: Use external symbols for scratch buffer
We were passing the scratch buffer address to the shaders via user sgprs,
but now we use external symbols and have the driver patch the shader
using reloc information.

llvm-svn: 226586
2015-01-20 17:49:47 +00:00
Tom Stellard 8255af45cb R600/SI: Add kill flag when copying scratch offset to a register
This allows us to re-use the same register for the scratch offset
when accessing large private arrays.

llvm-svn: 226585
2015-01-20 17:49:45 +00:00
Tom Stellard 8058069529 R600/SI: Don't store scratch buffer frame index in MUBUF offset field
We don't have a good way of legalizing this if the frame index offset
is more than the 12-bits, which is size of MUBUF's offset field, so
now we store the frame index in the vaddr field.

llvm-svn: 226584
2015-01-20 17:49:43 +00:00
Tom Stellard 1106b1c662 R600/SI: Update SIInstrInfo:verifyInstruction() after r225662
Now that we have our own custom register operand types, we need
to handle them in the verifiier.

llvm-svn: 226583
2015-01-20 17:49:41 +00:00
Rafael Espindola 2658554aec Add r224985 back with fixes.
The fixes are to note that AArch64 has additional restrictions on when local
relocations can be used. In particular, ld64 requires that relocations to
cstring/cfstrings use linker visible symbols.

Original message:

In an assembly expression like

bar:
  .long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

llvm-svn: 226503
2015-01-19 21:11:14 +00:00
David Blaikie 9459832ebd std::unique_ptrify the MCStreamer argument to createAsmPrinter
llvm-svn: 226414
2015-01-18 20:29:04 +00:00
Matt Arsenault eeb2a7e688 R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
llvm-svn: 226230
2015-01-15 23:58:35 +00:00
Matt Arsenault 268757ba60 R600/SI: Fix trailing comma with modifiers
Instructions with 1 operand can still use source modifiers,
so make sure we don't print an extra comma afterwards.

llvm-svn: 226226
2015-01-15 23:17:03 +00:00
Marek Olsak f0b130ace0 R600/SI: Unify VOP2 instructions which are VOP3-only on VI
This removes some duplicated classes and definitions.

These instructions are defined:
  _e32 // pseudo
  _e32_si
  _e64 // pseudo
  _e64_si
  _e64_vi

llvm-svn: 226191
2015-01-15 18:43:06 +00:00
Marek Olsak c536850526 R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI
llvm-svn: 226190
2015-01-15 18:43:01 +00:00
Marek Olsak 15e4a59899 R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
These are VOP3-only on VI.

The new multiclass doesn't define VOP3 versions of VOP2 instructions.

llvm-svn: 226189
2015-01-15 18:42:55 +00:00
Marek Olsak a93603d508 R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
v2: modify hasVALU32BitEncoding instead
v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both
      hasVALU32BitEncoding and AMDGPUMCInstLower::lower
    - report an error if a pseudo can't be lowered
llvm-svn: 226188
2015-01-15 18:42:51 +00:00
Marek Olsak dc4d202f10 R600/SI: Add common class VOPAnyCommon
llvm-svn: 226187
2015-01-15 18:42:44 +00:00
Marek Olsak eae20ab5fd R600/SI: Don't select SI-only VOP3 opcodes on VI
llvm-svn: 226186
2015-01-15 18:42:40 +00:00
Rafael Espindola 7244bb3c17 Revert "Add r224985 back with two fixes."
This reverts commit r225644 while I debug a regression.

llvm-svn: 226022
2015-01-14 19:07:23 +00:00
Tom Stellard 0febe685ed R600/SI: Use IMPLICIT_DEF and KILL when failing to spill VGPRs
This helps us avoid 'invalid register class for operand' verifier
errors.

llvm-svn: 225989
2015-01-14 15:42:34 +00:00
Tom Stellard 42fb60e1a7 R600/SI: Spill VGPRs to scratch space for compute shaders
llvm-svn: 225988
2015-01-14 15:42:31 +00:00
Chandler Carruth d9903888d9 [cleanup] Re-sort all the #include lines in LLVM using
utils/sort_includes.py.

I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.

llvm-svn: 225974
2015-01-14 11:23:27 +00:00
Matt Arsenault e698663687 R600/SI: Fix bad code with unaligned byte vector loads
Don't do the v4i8 -> v4f32 combine if the load will need to
be expanded due to alignment. This stops adding instructions
to repack into a single register that the v_cvt_ubyteN_f32
instructions read.

llvm-svn: 225926
2015-01-14 01:35:22 +00:00
Matt Arsenault bd22342322 Implement new way of expanding extloads.
Now that the source and destination types can be specified,
allow doing an expansion that doesn't use an EXTLOAD of the
result type. Try to do a legal extload to an intermediate type
and extend that if possible.

This generalizes the special case custom lowering of extloads
R600 has been using to work around this problem.

This also happens to fix a bug that would incorrectly use more
aligned loads than should be used.

llvm-svn: 225925
2015-01-14 01:35:17 +00:00
Tom Stellard ae38f30d7b R600/SI: Define a schedule model
The machine scheduler is still disabled by default.

The schedule model is not complete yet, and could be improved.

llvm-svn: 225913
2015-01-14 01:13:19 +00:00
Tom Stellard fb77f00be8 R600/SI: Add pattern for bitcasting fp immediates to integers
The backend now assumes that all immediates are integers.  This allows
us to simplify immediate handling code, becasue we no longer need to
handle fp and integer immediates differently.

llvm-svn: 225844
2015-01-13 22:59:41 +00:00
Matt Arsenault bf0db918b2 R600: Implement getRecipEstimate
This requires a new hook to prevent expanding sqrt in terms
of rsqrt and reciprocal. v_rcp_f32, v_rsq_f32, and v_sqrt_f32 are
all the same rate, so this expansion would just double the number
of instructions and cycles.

llvm-svn: 225828
2015-01-13 20:53:23 +00:00
Matt Arsenault e93d06a579 R600: Implement getRsqrtEstimate
Only do for f32 since I'm unclear on both what this is expecting
for the refinement steps in terms of accuracy, and what
f64 instruction actually provides.

llvm-svn: 225827
2015-01-13 20:53:18 +00:00
Matt Arsenault b56d843348 R600: Make cttz / ctlz cheap to speculate
Speculating things is generally good. SI+ has instructions for these
for 32-bit values. This is still probably better even with the expansion
for 64-bit values, although it is odd that this callback doesn't have
the size as a parameter.

llvm-svn: 225822
2015-01-13 19:46:48 +00:00
Matt Arsenault 64dae8354b R600/SI: Remove redundant setting expand on f64 vectors
None of these are legal types already, so they default to
Expand.

llvm-svn: 225728
2015-01-12 23:13:00 +00:00
Tom Stellard b6550529a6 R600/SI: Use RegisterOperands to specify which operands can accept immediates
There are some operands which can take either immediates or registers
and we were previously using different register class to distinguish
between operands that could take immediates and those that could not.

This patch switches to using RegisterOperands which should simplify the
backend by reducing the number of register classes and also make it
easier to implement the assembler.

llvm-svn: 225662
2015-01-12 19:33:18 +00:00
Rafael Espindola d9c3e308f5 Add r224985 back with two fixes.
One is that AArch64 has additional restrictions on when local relocations can
be used. We have to take those into consideration when deciding to put a L
symbol in the symbol table or not.

The other is that ld64 requires the relocations to cstring to use linker
visible symbols on AArch64.

Thanks to Michael Zolotukhin for testing this!

Remove doesSectionRequireSymbols.

In an assembly expression like

bar:
.long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

llvm-svn: 225644
2015-01-12 18:13:07 +00:00
Tom Stellard 654d669e56 R600/SI: Remove SIISelLowering::legalizeOperands()
Its functionality has been replaced by calling
SIInstrInfo::legalizeOperands() from
SIISelLowering::AdjstInstrPostInstrSelection() and running the
SIFoldOperands and SIShrinkInstructions passes.

llvm-svn: 225445
2015-01-08 15:08:17 +00:00
Ahmed Bougacha 2b6917b020 [SelectionDAG] Allow targets to specify legality of extloads' result
type (in addition to the memory type).

The *LoadExt* legalization handling used to only have one type, the
memory type.  This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.

However, this isn't always the case.  For instance, on X86, with AVX,
this is legal:
    v4i32 load, zext from v4i8
but this isn't:
    v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.

Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.

Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.

Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior.  The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)

No functional change intended.

Differential Revision: http://reviews.llvm.org/D6532

llvm-svn: 225421
2015-01-08 00:51:32 +00:00
Tom Stellard 0599297cb4 R600/SI: Commute instructions to enable more folding opportunities
llvm-svn: 225410
2015-01-07 22:44:19 +00:00
Tom Stellard 26cc18df43 R600/SI: Only fold immediates that have one use
Folding the same immediate into multiple instruction will increase
program size, which can hurt performance.

llvm-svn: 225405
2015-01-07 22:18:27 +00:00
Tom Stellard 45c0b3a882 R600/SI: Remove VReg_32 register class
Use VGPR_32 register class instead.  These two register classes were
identical and having separate classes was causing
SIInstrInfo::isLegalOperands() to be overly conservative in some cases.

This change is necessary to prevent future paches from missing a folding
opportunity in fneg-fabs.ll.

llvm-svn: 225382
2015-01-07 20:59:25 +00:00
Tom Stellard 4842c05216 R600/SI: Add a V_MOV_B64 pseudo instruction
This is used to simplify the SIFoldOperands pass and make it easier to
fold immediates.

llvm-svn: 225373
2015-01-07 20:27:25 +00:00
Tom Stellard ef3b864a07 R600/SI: Teach SIFoldOperands to split 64-bit constants when folding
This allows folding of sequences like:

s[0:1] = s_mov_b64 4
v_add_i32 v0, s0, v0
v_addc_u32 v1, s1, v1

into

v_add_i32 v0, 4, v0
v_add_i32 v1, 0, v1

llvm-svn: 225369
2015-01-07 19:56:17 +00:00
Tom Stellard bb763e6b47 R600/SI: Refactor SIFoldOperands to simplify immediate folding
This will make a future patch much less intrusive.

llvm-svn: 225358
2015-01-07 17:42:16 +00:00
Matt Arsenault d0101a2dfd R600/SI: Add combine for isinfinite pattern
llvm-svn: 225310
2015-01-06 23:00:46 +00:00
Matt Arsenault 6f6233dc58 R600/SI: Pattern match isinf to v_cmp_class instructions
llvm-svn: 225307
2015-01-06 23:00:41 +00:00
Matt Arsenault f2290336b7 R600/SI: Add basic DAG combines for fp_class
llvm-svn: 225306
2015-01-06 23:00:39 +00:00
Matt Arsenault 4831ce5491 R600/SI: Add class intrinsic
llvm-svn: 225305
2015-01-06 23:00:37 +00:00
Tom Stellard 9d6797ae58 R600/SI: Insert s_waitcnt before s_barrier instructions.
This ensures that all memory operations are complete when all threads
reach the barrier.

llvm-svn: 225290
2015-01-06 19:52:07 +00:00
Tom Stellard b3931b814a R600/SI: Fix dependency calculation for DS writes instructions in SIInsertWaits
In DS write instructions, the address operand comes before the value
operand(s) which is reversed from every other instruction type.

The SIInsertWait assumed that the first use for each instruction
was the value, so for DS write it was protecting the address
operand with s_waitcnt instructions when it should have been
protecting the value operand.

llvm-svn: 225289
2015-01-06 19:52:04 +00:00
Tom Stellard 49f8bfdcb7 R600/SI: Add a stub GCNTargetMachine
This is equivalent to the AMDGPUTargetMachine now, but it is the
starting point for separating R600 and GCN functionality into separate
targets.

It is recommened that users start using the gcn triple for GCN-based
GPUs, because using the r600 triple for these GPUs will be deprecated in
the future.

llvm-svn: 225277
2015-01-06 18:00:21 +00:00
Tom Stellard 4bc014f0a7 R600/SI: Remove MachineFunction dump from AsmPrinter
The dump was dependent on a feature string, which meant that it couldn't
be disabled or enable on a per compile basis.

llvm-svn: 225275
2015-01-06 17:59:56 +00:00
Lang Hames 04b37c4043 Revert r225048: It broke ObjC on AArch64.
I've filed http://llvm.org/PR22100 to track this issue.

llvm-svn: 225228
2015-01-06 00:54:32 +00:00
Craig Topper 589ceee7f4 Minor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers.
Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation.

llvm-svn: 225114
2015-01-03 08:16:34 +00:00
Rafael Espindola 54b435ec3c Add r224985 back with a fix.
The issues was that AArch64 has additional restrictions on when local
relocations can be used. We have to take those into consideration when
deciding to put a L symbol in the symbol table or not.

Original message:

Remove doesSectionRequireSymbols.

In an assembly expression like

bar:
.long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

llvm-svn: 225048
2014-12-31 17:19:34 +00:00
Rafael Espindola d4da9040de Revert "Remove doesSectionRequireSymbols."
This reverts commit r224985.

I am investigating why it made an Apple bot unhappy.

llvm-svn: 225044
2014-12-31 16:06:48 +00:00
Rafael Espindola b22d5aa49a Remove doesSectionRequireSymbols.
In an assembly expression like

bar:
.long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

llvm-svn: 224985
2014-12-30 13:13:27 +00:00
Matt Arsenault 22b4c256e1 Enable (sext x) == C --> x == (trunc C) combine
Extend the existing code which handles this for zext. This makes this
more useful for targets with ZeroOrNegativeOne BooleanContent and
obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne)
since the constant will now be shrunk to i1.

llvm-svn: 224691
2014-12-21 16:48:42 +00:00
Matt Arsenault 013ddaf18c R600: Remove outdated comment
llvm-svn: 224648
2014-12-19 23:29:13 +00:00
Matt Arsenault dc10307524 R600/SI: Only form min/max with 1 use.
If the condition is used for something else, this increases
the number of instructions.

llvm-svn: 224646
2014-12-19 23:15:30 +00:00
Tom Stellard 5352f35a89 R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructions
The constant bus restrictions only apply to VALU instructions.  This
enables SIFoldOperands to fold immediates into SALU instructions.

llvm-svn: 224623
2014-12-19 22:15:37 +00:00
Tom Stellard c3d7eeb6e5 R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand
mubuf instructions now define the soffset field using the SCSrc_32
register class which indicates that only SGPRs and inline constants
are allowed.

llvm-svn: 224622
2014-12-19 22:15:30 +00:00
Matt Arsenault 303011a005 R600/SI: Fix f64 inline immediates
llvm-svn: 224458
2014-12-17 21:04:08 +00:00
Matt Arsenault 1e3a4ebc6e R600: Fix min/max matching problems with unordered compares
The returned operand needs to be permuted for the unordered
compares. Also fix incorrectly producing fmin_legacy / fmax_legacy
for f64, which don't exist.

llvm-svn: 224094
2014-12-12 02:30:37 +00:00
Matt Arsenault 145d5717f5 R600/SI: fmin/fmax_legacy are not associative
llvm-svn: 224093
2014-12-12 02:30:33 +00:00
Matt Arsenault 477b178276 R600/SI: Don't promote f32 select to i32
This is nice for the instruction patterns, but it complicates
min / max matching. The select doesn't have the correct type and would
require looking through the bitcasts for the real float operands.

llvm-svn: 224092
2014-12-12 02:30:29 +00:00
Matt Arsenault 810cb62962 Add target hook for whether it is profitable to reduce load widths
Add an option to disable optimization to shrink truncated larger type
loads to smaller type loads. On SI this prevents using scalar load
instructions in some cases, since there are no scalar extloads.

llvm-svn: 224084
2014-12-12 00:00:24 +00:00
Matt Arsenault 102a70409e R600/SI: Handle physical registers in getOpRegClass
llvm-svn: 224079
2014-12-11 23:37:34 +00:00
Matt Arsenault e368cb378f R600/SI: Don't verify constant bus usage of flag ops
This was checking if pseudo-operands like the source
modifiers were using the constant bus, which happens to work
because the values these all can be happen to be valid inline
immediates.

This fixes a later commit which starts checking the register class
of the operands.

llvm-svn: 224078
2014-12-11 23:37:32 +00:00
Matt Arsenault 58d502f0d4 R600/SI: Use unordered equal instructions
llvm-svn: 224067
2014-12-11 22:15:43 +00:00
Matt Arsenault 8b989efaf9 R600/SI: Make more unordered comparisons legal
This saves a second compare and an and / or by using
the unordered comparison instructions.

llvm-svn: 224066
2014-12-11 22:15:39 +00:00
Matt Arsenault 9cded7a74b R600/SI: Use unordered not equal instructions
llvm-svn: 224065
2014-12-11 22:15:35 +00:00
Matthias Braun 7e37a5f523 [CodeGen] Add print and verify pass after each MachineFunctionPass by default
Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.

To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.

This is the 2nd attempt at this after realizing that PassManager::add() may
actually delete the pass.

llvm-svn: 224059
2014-12-11 21:26:47 +00:00
Rafael Espindola 01c73610d0 This reverts commit r224043 and r224042.
check-llvm was failing.

llvm-svn: 224045
2014-12-11 20:03:57 +00:00
Matthias Braun a7c82a9f1d [CodeGen] Add print and verify pass after each MachineFunctionPass by default
Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.

To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.

llvm-svn: 224042
2014-12-11 19:42:05 +00:00
Marek Olsak 0c05645b0f R600/SI: Use getTargetConstant in AdjustRegClass
llvm-svn: 223940
2014-12-10 19:25:31 +00:00
Tom Stellard 3e41dc419c R600/SI: Set MayStore = 0 on MUBUF loads
llvm-svn: 223722
2014-12-09 00:03:54 +00:00
Tom Stellard 3260ec41cf R600/SI: Move setting of the lds bit to the base MUBUF class
llvm-svn: 223721
2014-12-09 00:03:51 +00:00
Matt Arsenault 13bd95bbc7 R600/SI: Move continue after checking s_mov_b32.
There's nothing else to bother trying to shrink these.

llvm-svn: 223686
2014-12-08 19:55:43 +00:00
Marek Olsak fa58e5e111 R600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOP
This is only a workaround.

llvm-svn: 223615
2014-12-07 17:17:43 +00:00
Marek Olsak 58f61a84e7 R600/SI: Set 20-bit immediate byte offset for SMRD on VI
llvm-svn: 223614
2014-12-07 17:17:38 +00:00
Marek Olsak be047806d1 R600/SI: Update instruction conversions for VI
There are 3 changes:
- Convert 32-bit S_LSHL/LSHR/ASHR to their V_*REV variants for VI
- Lower RSQ_CLAMP for VI
- Don't generate MIN/MAX_LEGACY on VI

llvm-svn: 223604
2014-12-07 12:19:03 +00:00
Marek Olsak 5df00d63e2 R600/SI: Add VI instructions
llvm-svn: 223603
2014-12-07 12:18:57 +00:00
Marek Olsak b08604c4cd R600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes
llvm-svn: 223602
2014-12-07 12:18:45 +00:00
Tom Stellard 8d5f5e4238 R600/SI: Restore PrivateGlobalPrefix to the default ELF value of ".L"
This was changed in r223323.

llvm-svn: 223579
2014-12-06 05:34:34 +00:00
Matt Arsenault 4e27343eec Allow target to specify prefix for labels
Use the MCAsmInfo instead of the DataLayout, and allow
specifying a custom prefix for labels specifically. HSAIL
requires that labels begin with @, but global symbols with &.

llvm-svn: 223323
2014-12-04 00:06:57 +00:00
Tom Stellard 05cd445c4d R600/SI: Move SIInsertWaits into AMDGPUPassConfig::addPreSched2()
This pass needs to be run after PrologEpilogInserter, because
that pass may inserter spill code which reads or writes memory.

llvm-svn: 223253
2014-12-03 18:27:08 +00:00
Tom Stellard 92105e87e8 R600/SI: Don't run SI passes on R600 subtargets
llvm-svn: 223252
2014-12-03 18:27:05 +00:00
Aaron Ballman d58a1f4d98 Silencing a 32-bit implicit conversion warning in MSVC; NFC.
llvm-svn: 223237
2014-12-03 14:39:58 +00:00
Matt Arsenault 120a0c92f4 R600/SI: Fix SIFixSGPRCopies for copies to physical registers
This shows up when operands required to be passed in VCC are copied
to.

llvm-svn: 223208
2014-12-03 05:22:39 +00:00
Matt Arsenault 88652a009b R600/SI: Remove incorrect assertion
This can be a COPY to a physical register, such as VCC

llvm-svn: 223207
2014-12-03 05:22:38 +00:00
Matt Arsenault becd656c7c R600/SI: Remove i1 pseudo VALU ops
Select i1 logical ops directly to 64-bit SALU instructions.
Vector i1 values are always really in SGPRs, with each
bit for each item in the wave. This saves about 4 instructions
when and/or/xoring any condition, and also helps write conditions
that need to be passed in vcc.

This should work correctly now that the SGPR live range
fixing pass works. More work is needed to eliminate the VReg_1
pseudo regclass and possibly the entire SILowerI1Copies pass.

llvm-svn: 223206
2014-12-03 05:22:35 +00:00
Matt Arsenault 2f470c62cb R600/SI: Fix suspicious indexing
The loop is over the operands of an instruction, and checks the
register with the sub reg index of the dest register. This probably
meant to be checking the sub reg index of the same operand.

llvm-svn: 223205
2014-12-03 05:22:32 +00:00
Matt Arsenault 691ae3d657 R600/SI: Fix running SILowerI1Copies a second time
llvm-svn: 223204
2014-12-03 05:22:30 +00:00
Matt Arsenault 0d2832ae8d R600/SI: Fix live range error hidden by SIFoldOperands
m0 is treated as a virtual register class with a single register
rather than the physical register it really is. This was updating
the live range of the used virtual copy of m0 from the first ds_read
instruction, and leaving the unused copy unchanged. This resulted in a
"Live segment doesn't end at a valid instruction" verifier error because
the erased instructions. Update the live range of the second copy (which
should be dead).

No test since I'm not sure how to trigger this with SIFoldOperands
enabled.

llvm-svn: 223203
2014-12-03 05:22:29 +00:00
Tom Stellard 369308061b R600/SI: Enable inline assembly
We just needed to remove the assertion in
AMDGPURegisterInfo::getFrameRegister(), which is called when
initializing the parser for inline assembly.

llvm-svn: 223197
2014-12-03 04:08:00 +00:00
Matt Arsenault fb13b22d9a R600/SI: Change mubuf offsets to print as decimal
This matches SC's behavior.

llvm-svn: 223194
2014-12-03 03:12:13 +00:00
Tom Stellard b8fd6eff89 R600/SI: Emit amd_kernel_code_t header for AMDGPU environment
llvm-svn: 223160
2014-12-02 22:00:07 +00:00
Tom Stellard 4df465bd5e R600/SI: Move more information into SIProgramInfo struct
llvm-svn: 223154
2014-12-02 21:28:53 +00:00
Tom Stellard ab256185da R600/SI: Refactor AMDGPUAsmPrinter::EmitProgramInfoSI()
llvm-svn: 223144
2014-12-02 19:45:05 +00:00
Tom Stellard feab91cac3 R600/SI: Set correct number of user sgprs for HSA runtime
We don't support scratch buffers yet with HSA.

llvm-svn: 223130
2014-12-02 17:41:43 +00:00
Tom Stellard 794c8c0f78 R600/SI: Set the ATC bit on all resource descriptors for the HSA runtime
llvm-svn: 223125
2014-12-02 17:05:41 +00:00
Matt Arsenault c5f174d060 R600/SI: Various instruction format bit test cleanups
- Fix missing SALU format bits
- Remove unused isSALUInstr
- Add isVALU
- Switch isDS to use a bit like the others
- Move SIInstrInfo::is* functions to header
- Reorder so they are approximately sorted by type (SALU, VALU, memory)

llvm-svn: 223038
2014-12-01 15:52:46 +00:00
Matt Arsenault 8596f71910 R600/SI: Fix assertion on sign extend of 3 vectors
This was trying to create an MVT with 3x vectors which
created an invalid EVT

llvm-svn: 222942
2014-11-28 22:51:38 +00:00
Matt Arsenault fcdddf9602 R600/SI: Use ZeroOrNegativeOneBooleanContent
This sort of doesn't matter since the setcc type is i1, but
this previously was using the default UndefinedBooleanContent. This
makes it more consistent with R600. This enables more optimizations
which typically give up on UndefinedBooleanContent. For example,
there is already a special case target DAG combine for
setcc + sext which can be eliminated in favor of what the generic
DAG combiner can do if it assumes boolean values are sign extended.
Since -1 is an inline immediate, using it is basically free and the
backend already uses it when a boolean value is needed in a wider type.

llvm-svn: 222850
2014-11-26 21:23:15 +00:00
Matt Arsenault b935089576 R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies
This fixes moving boolean constants into registers before operating
on them. They get permuted and shrunk down to e32 anyway later. This
is a temporary fix until the patch that removes these pseudos is
committed.

llvm-svn: 222844
2014-11-26 18:18:28 +00:00
Craig Topper c50d64b07b Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
llvm-svn: 222801
2014-11-26 00:46:26 +00:00
Matt Arsenault 3896a0a99c R600/SI: Only use one DEBUG()
llvm-svn: 222789
2014-11-25 21:03:22 +00:00
Chandler Carruth 4c8cf4f7bc Revert r222746: That commit did not update any tests and caused two R600
tests to start failing.

Original commit log: R600/SI: Disable commutativity for MIN/MAX_LEGACY

llvm-svn: 222753
2014-11-25 10:50:41 +00:00
Marek Olsak f1449e99b9 R600/SI: Disable commutativity for MIN/MAX_LEGACY
llvm-svn: 222746
2014-11-25 09:49:23 +00:00
Matt Arsenault e335fd343e R600/SI: Fix allocating flat_scr_lo / flat_scr_hi
Only the super register flat_scr was marked as reserved,
so in some cases with high register usage it would still
try to allocate the subregisters.

llvm-svn: 222737
2014-11-25 07:53:06 +00:00
Aaron Ballman 41580deaf1 Removing a variable that is initialized but never read. The original author has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime.
llvm-svn: 222649
2014-11-24 14:03:16 +00:00
Matt Arsenault 2a495975ed R600: Fix extloads of i1 on R600/Evergreen
llvm-svn: 222631
2014-11-23 02:57:54 +00:00
Matt Arsenault 28638f1e2c R600: Fix assert on copy of an i1 on pre-SI
i1 is not a legal type on Evergreen, so this combine proceeded
and tried to produce a bitcast between i1 and i8.

llvm-svn: 222630
2014-11-23 02:57:52 +00:00
Tom Stellard 91c7ef529d R600/SI: Add an s_mov_b32 to patterns which use the M0RegClass
We need to use a s_mov_b32 rather than a copy, so that CSE will
eliminate redundant moves to the m0 register.

llvm-svn: 222584
2014-11-21 22:31:46 +00:00
Tom Stellard a99ada528c R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
This s_mov_b32 will write to a virtual register from the M0Reg
class and all the ds instructions now take an extra M0Reg explicit
argument.

This change is necessary to prevent issues with the scheduler
mixing together instructions that expect different values in the m0
registers.

llvm-svn: 222583
2014-11-21 22:31:44 +00:00
Tom Stellard 6596ba7933 R600/SI: Add SIFoldOperands pass
This pass attempts to fold the source operands of mov and copy
instructions into their uses.

llvm-svn: 222581
2014-11-21 22:06:37 +00:00
Tom Stellard fb0011cf1a R600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializable
llvm-svn: 222579
2014-11-21 22:00:16 +00:00
Tom Stellard e0ddfd11ea R600/SI: Make SIInstrInfo::isOperandLegal() more strict
A register operand that has a common sub-class with its instruction's
defined register class is not always legal.  For example,
SReg_32 and M0Reg both have a common sub-class, but we can't
use an SReg_32 in instructions that expect a M0Reg.

This prevents the llvm.SI.sendmsg.ll test from failing when the fold
operand pass is added.

llvm-svn: 222368
2014-11-19 16:58:49 +00:00
Matt Arsenault c09cc3c5b0 R600/SI: Implement areMemAccessesTriviallyDisjoint
This partially makes up for not having address spaces
used for alias analysis in some simple cases.

This is not yet enabled by default so shouldn't change anything yet.

llvm-svn: 222286
2014-11-19 00:01:31 +00:00
Matt Arsenault 9a072c19ae R600/SI: Set hasSideEffects = 0 on load and store instructions.
Assuming unmodeled side effects interferes with some scheduling
opportunities.

Don't put it in the base class of DS instructions since there
are a few weird effecting, non load/store instructions there.

llvm-svn: 222285
2014-11-18 23:57:33 +00:00
Matt Arsenault 162c1010bd R600/SI: Move SIFixSGPRCopies to inst selector passes
This should expose more of the actually used VALU
instructions to the machine optimization passes.

This also should help getting i1 handling into a better state.
For not entirly understood reasons, this fixes the split-scalar-i64-add.ll
test where a 64-bit add would only partially be moved to the VALU
resulting in use of undefined VCC.

llvm-svn: 222256
2014-11-18 21:06:58 +00:00
Tom Stellard f0a2107c6b R600/SI: Make sure resource descriptors are always stored in SGPRs
llvm-svn: 222253
2014-11-18 20:39:39 +00:00
Matt Arsenault 7480a0e163 R600/SI: Don't copy flags when extracting subreg
This was resulting in use of a register after a kill.
For some reason this showed up as a problem in many tests
when moving the SIFixSGPRCopies pass closer to instruction
selection.

llvm-svn: 222175
2014-11-17 21:11:37 +00:00
Matt Arsenault 6f679785f4 R600/SI: Assume SIFixSGPRCopies makes changes
I'm not sure if this was breaking anything.

llvm-svn: 222174
2014-11-17 21:11:34 +00:00
Craig Topper 7f416c8acb Convert some EVTs to MVTs where only a SimpleValueType is needed.
llvm-svn: 222109
2014-11-16 21:17:18 +00:00
Matt Arsenault 36094d788a R600: Permute operands when selecting legacy min/max
This gets the correct NaN behavior based on the compare type
the hardware uses. This now passes the new piglit test I have
for this on SI.

Add stricter tests for the operand order.

llvm-svn: 222079
2014-11-15 05:02:57 +00:00
Tom Stellard 83171b32ed R600: Fix 64-bit integer division
This fixes a failure in one of the oclconform tests.

Patch by: Jan Vesely

llvm-svn: 222073
2014-11-15 01:07:57 +00:00
Tom Stellard bf69d76106 R600: Factor i64 UDIVREM lowering into its own fuction
This is so it could potentially be used by SI.  However, the current
implementation does not always produce correct results, so the
IntegerDivisionPass is being used instead.

llvm-svn: 222072
2014-11-15 01:07:53 +00:00
Tom Stellard e63d5ed2f9 R600/SI: Mark s_movk_i32 as rematerializable
llvm-svn: 222037
2014-11-14 20:43:28 +00:00
Tom Stellard bdd567d86d R600/SI: Fix spilling of m0 register
If we have spilled the value of the m0 register, then we need to restore
it with v_readlane_b32 to a regular sgpr, because v_readlane_b32 can't
write to m0.

v_readlane_b32 can't write to m0, so

llvm-svn: 222036
2014-11-14 20:43:26 +00:00
Matt Arsenault cc3c2b3946 R600/SI: Combine min3/max3 instructions
llvm-svn: 222032
2014-11-14 20:08:52 +00:00
Matt Arsenault 72858935f7 R600/SI: Fix verifier error from a branch on IMPLICIT_DEF
SIILowerI1Copies wasn't correctly handling this case.

llvm-svn: 222020
2014-11-14 18:43:41 +00:00
Matt Arsenault 6ad34266e3 Fix unused variable warning without asserts
llvm-svn: 222017
2014-11-14 18:40:49 +00:00
Matt Arsenault d28a7fde32 R600/SI: Match integer min / max instructions
llvm-svn: 222015
2014-11-14 18:30:06 +00:00
Matt Arsenault 94812216ef R600/SI: Use S_BFE_I64 for 64-bit sext_inreg
llvm-svn: 222012
2014-11-14 18:18:16 +00:00
Tom Stellard 9dec074399 R600/SI: Fix assembly names for exec_hi and exec_lo
llvm-svn: 221995
2014-11-14 14:08:04 +00:00
Tom Stellard 9d7ddd516e R600/SI: Start implementing an assembler
This was done using the Sparc and PowerPC AsmParsers as guides.  So far it
is very simple and only supports sopp instructions.

llvm-svn: 221994
2014-11-14 14:08:00 +00:00
Matt Arsenault 21c938e14b R600/SI: Make constant array static
llvm-svn: 221965
2014-11-14 02:21:58 +00:00