Commit Graph

1598 Commits

Author SHA1 Message Date
Matt Arsenault f07833057c R600/SI: Use v_madmk_f32
llvm-svn: 230149
2015-02-21 21:29:10 +00:00
Matt Arsenault 0325d3d27f R600/SI: Try to use v_madak_f32
This is a code size optimization when the constant
only has one use.

llvm-svn: 230148
2015-02-21 21:29:07 +00:00
Matt Arsenault 657b1cb739 R600/SI: Don't crash when getting immediate operand size
llvm-svn: 230147
2015-02-21 21:29:04 +00:00
Matt Arsenault 70120fa813 R600/SI: Fix mad*k definitions
llvm-svn: 230146
2015-02-21 21:29:00 +00:00
Tim Northover 3b6b7ca2bc CodeGen: convert CCState interface to using ArrayRefs
Everyone except R600 was manually passing the length of a static array
at each callsite, calculated in a variety of interesting ways. Far
easier to let ArrayRef handle that.

There should be no functional change, but out of tree targets may have
to tweak their calls as with these examples.

llvm-svn: 230118
2015-02-21 02:11:17 +00:00
Matt Arsenault 20711b7bae R600/SI: Remove v_sub_f64 pseudo
The expansion code does the same thing. Since
the operands were not defined with the correct
types, this has the side effect of fixing operand
folding since the expanded pseudo would never use
SGPRs or inline immediates.

llvm-svn: 230072
2015-02-20 22:10:45 +00:00
Matt Arsenault 8d6300346f R600: Use new fmad node.
This enables a few useful combines that used to only
use fma.

Also since v_mad_f32 apparently does not support denormals,
disable the existing cases that are custom handled if they are
requested.

llvm-svn: 230071
2015-02-20 22:10:41 +00:00
Michael Kuperstein efd7a96d2e Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.
llvm-svn: 229841
2015-02-19 11:38:11 +00:00
Michael Kuperstein ba5b04c798 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.

No functional change.

Differential Revision: http://reviews.llvm.org/D7065

llvm-svn: 229831
2015-02-19 09:01:04 +00:00
Eric Christopher 0795a2ef0c Remove a few more calls to TargetMachine::getSubtarget from the
R600 port.

llvm-svn: 229804
2015-02-19 01:10:55 +00:00
Eric Christopher 7edca437f5 Grab the subtarget off of the machine function for the R600
asm printer and clean up a bunch of uses.

llvm-svn: 229803
2015-02-19 01:10:53 +00:00
Eric Christopher 96caeda730 Remove the DisasmEnabled AsmPrinter variable and just look it
up on the subtarget where it's set anyhow than looking it up
2-3 times in the same place.

llvm-svn: 229802
2015-02-19 01:10:49 +00:00
Eric Christopher 111de895a0 80-column fixups.
llvm-svn: 229789
2015-02-19 00:15:33 +00:00
Marek Olsak 9b8f32eed1 R600/SI: Fix READLANE and WRITELANE lane select for VI
VOP2 declares vsrc1, but VOP3 declares src1.
We can't use the same "ins" if the operands have different names in VOP2
and VOP3 encodings.

This fixes a hang in geometry shaders which spill M0 on VI.
(BTW it doesn't look like M0 needs spilling and the spilling seems
duplicated 3 times)

llvm-svn: 229752
2015-02-18 22:12:45 +00:00
Marek Olsak 8eeebcccb5 R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_C
llvm-svn: 229751
2015-02-18 22:12:41 +00:00
Marek Olsak b8c818337d R600/SI: Remove explicit VOP operand checking
This should be handled by the OperandType checking.

llvm-svn: 229750
2015-02-18 22:12:37 +00:00
Tom Stellard 1ca873bbc5 R600/SI: Don't set isCodeGenOnly = 1 on all instructions
We only need to set this on pseudo instructions which won't
be used by the assembler.

llvm-svn: 229689
2015-02-18 16:08:17 +00:00
Tom Stellard c34c37ae66 R600/SI: Add missing VOP1 instructions
llvm-svn: 229688
2015-02-18 16:08:15 +00:00
Tom Stellard 894b9883f4 R600/SI: Add missing VOP2 instructions
llvm-svn: 229687
2015-02-18 16:08:14 +00:00
Tom Stellard 0c0008cb6e R600/SI: Add definition for S_CBRANCH_G_FORK
llvm-svn: 229686
2015-02-18 16:08:13 +00:00
Tom Stellard ce449ade7e R600/SI: Add missing SOP1 instructions
llvm-svn: 229685
2015-02-18 16:08:11 +00:00
Tom Stellard ee21faa029 R600/SI: Refactor SOP2 definitions
llvm-svn: 229684
2015-02-18 16:08:09 +00:00
Matt Arsenault 0ba644b66b R600/SI: Rename dst encoding field to be consistent with docs
The docs call this vdst instead of just dst.

llvm-svn: 229614
2015-02-18 02:15:37 +00:00
Matt Arsenault e3dbcf6656 R600/SI: Consistently capitalize encoding field names
Some formats capitalized these, but most didn't. Change
them all to be consistently lowercase.

Now, non-encoding fields and convenience bits are capitalized.
Also remove weird looking empty line in some of the formats.

llvm-svn: 229613
2015-02-18 02:15:35 +00:00
Matt Arsenault 1ecac06a6f R600/SI: Set noNamedPositionallyEncodedOperands
llvm-svn: 229612
2015-02-18 02:15:32 +00:00
Matt Arsenault 096ec1e10c R600/SI: Fix src1_modifiers for class instructions
src1 doesn't have modifiers, but the operand was missing
resulting in an encoding build error when all fields
are required.'

llvm-svn: 229611
2015-02-18 02:15:30 +00:00
Matt Arsenault 65fa1c425d R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
Rename the multiclass since it now applies to the output
modifiers as well.

llvm-svn: 229610
2015-02-18 02:15:27 +00:00
Matt Arsenault 284d7dfb53 R600: Fix operand encoding error
llvm-svn: 229609
2015-02-18 02:10:42 +00:00
Matt Arsenault 1991f5e40b R600/SI: Fix encoding error from glc bit on VI SMRD instructions
llvm-svn: 229608
2015-02-18 02:10:40 +00:00
Matt Arsenault e6c5241814 R600/SI: Fix operand encoding for flat instructions
llvm-svn: 229607
2015-02-18 02:10:37 +00:00
Matt Arsenault 07e3bb153f R600/SI: Fix error from vdst on no return atomics
Set the ignored field to 0 so we can enable
noNamedPositionallyEncodedOperands.

llvm-svn: 229606
2015-02-18 02:10:35 +00:00
Matt Arsenault caa1288fff R600/SI: Add missing offset operand to buffer bothen
llvm-svn: 229605
2015-02-18 02:04:38 +00:00
Matt Arsenault 2ad8bab7ee R600/SI: Add missing soffset operand to global atomics
llvm-svn: 229604
2015-02-18 02:04:35 +00:00
Matt Arsenault 3c34ae293c R600/SI: Fix brace identation
llvm-svn: 229603
2015-02-18 02:04:31 +00:00
Tom Stellard 7b3aa88ac1 R600/SI: Fix asam errors in SIFoldOperands
We were trying to fold into implicit uses, which led to out of bounds
access of the MCInstrDesc::OpInfo arrray.

llvm-svn: 229533
2015-02-17 20:11:54 +00:00
Tom Stellard bc3776803b R600/SI: Extend private extload pattern to include zext loads
llvm-svn: 229507
2015-02-17 16:36:00 +00:00
Benjamin Kramer 6cd780ff21 Prefer SmallVector::append/insert over push_back loops.
Same functionality, but hoists the vector growth out of the loop.

llvm-svn: 229500
2015-02-17 15:29:18 +00:00
Andrew Trick 05938a5481 AArch64: Safely handle the incoming sret call argument.
This adds a safe interface to the machine independent InputArg struct
for accessing the index of the original (IR-level) argument. When a
non-native return type is lowered, we generate the hidden
machine-level sret argument on-the-fly. Before this fix, we were
representing this argument as OrigArgIndex == 0, which is an outright
lie. In particular this crashed in the AArch64 backend where we
actually try to access the type of the original argument.

Now we use a sentinel value for machine arguments that have no
original argument index. AArch64, ARM, Mips, and PPC now check for this
case before accessing the original argument.

Fixes <rdar://19792160> Null pointer assertion in AArch64TargetLowering

llvm-svn: 229413
2015-02-16 18:10:47 +00:00
Aaron Ballman f9a1897c72 Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for requiring the macro. NFC; LLVM edition.
llvm-svn: 229340
2015-02-15 22:54:22 +00:00
Matt Arsenault 0bbcd8ba2f R600/SI: Implement correct f64 fdiv
This version passes the OpenCL conformance test.

llvm-svn: 229239
2015-02-14 04:30:08 +00:00
Matt Arsenault 044f1d19cf R600/SI: Use complex operand folding for div_scale
llvm-svn: 229238
2015-02-14 04:24:28 +00:00
Matt Arsenault 1bc9d95047 R600/SI: Fix implicit vcc operand to v_div_fmas_*
This should allow finally fixing the f64 fdiv implementation.

Test is disabled for VI since there seems to be a problem with one
of the buffer load instructions on it.

llvm-svn: 229236
2015-02-14 04:22:00 +00:00
Matt Arsenault 6e26b8d854 R600/SI: Fix schedule model for v_div_scale_{f32|f64}
llvm-svn: 229235
2015-02-14 04:03:18 +00:00
Matt Arsenault 35733e2dec R600/SI: Really fix size of VReg_1
llvm-svn: 229234
2015-02-14 03:54:32 +00:00
Matt Arsenault 1bcc8cba5a R600/SI: Rename encoding field to match docs for VOP3b
llvm-svn: 229233
2015-02-14 03:54:29 +00:00
Matt Arsenault 31ec598a2a R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}
This apparently got lost in the VI changes.

llvm-svn: 229230
2015-02-14 03:40:35 +00:00
Matt Arsenault 692acf1438 R600/SI: Fix VOP3b encoding on VI
llvm-svn: 229228
2015-02-14 03:02:23 +00:00
Matt Arsenault 95546b46ab R600/SI: Fix phys reg copies in SIFoldOperands
llvm-svn: 229227
2015-02-14 02:55:57 +00:00
Matt Arsenault 9998168982 R600/SI: Fix copies from SGPR to VCC
This shows up without optimizations when vcc is required
to be used.

llvm-svn: 229226
2015-02-14 02:55:56 +00:00
Matt Arsenault 834b1aa806 R600/SI: Add hack to copy from a VGPR to VCC
This hopefully should be fixed when VReg_1 is removed.

llvm-svn: 229225
2015-02-14 02:55:54 +00:00