a9ac0e0f75
[SystemZ] Add comparisons of large immediates using high words
...
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.
llvm-svn: 191775
2013-10-01 14:56:23 +00:00
42a694f44e
[SystemZ] Add immediate addition involving high words
...
llvm-svn: 191774
2013-10-01 14:53:46 +00:00
2cac763544
[SystemZ] Extend test-under-mask support to high GR32s
...
llvm-svn: 191773
2013-10-01 14:41:52 +00:00
3ad5a15b72
[SystemZ] Extend 32-bit RISBG optimizations to high words
...
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.
llvm-svn: 191770
2013-10-01 14:36:20 +00:00
2896d044bd
[SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words
...
As the comment says, we always want to use STOC for 32-bit stores.
llvm-svn: 191767
2013-10-01 14:33:55 +00:00
d840745829
ARM: support interrupt attribute
...
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.
rdar://problem/14207019
llvm-svn: 191766
2013-10-01 14:33:28 +00:00
f6377fba4c
[SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and above
...
Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR
transfers are full-register transfers. This patch optimizes GPR<->FPR
float transfers when the high word of a GPR is directly accessible.
llvm-svn: 191764
2013-10-01 14:31:11 +00:00
d88b9832c8
Add non-blocking Wait() for launched processes
...
- New ProcessInfo class to encapsulate information about child processes.
- Generalized the Wait() to support non-blocking wait on child processes.
- ExecuteNoWait() now returns a ProcessInfo object with information about
the launched child. Users will be able to use this object to
perform non-blocking wait.
- ExecuteNoWait() now accepts an ExecutionFailed param that tells if execution
failed or not.
These changes will allow users to implement basic process parallel
tools.
Differential Revision: http://llvm-reviews.chandlerc.com/D1728
llvm-svn: 191763
2013-10-01 14:28:18 +00:00
7028428c2c
[SystemZ] Allow integer AND involving high words
...
llvm-svn: 191762
2013-10-01 14:20:41 +00:00
5718dacbdd
[SystemZ] Allow integer XOR involving high words
...
llvm-svn: 191759
2013-10-01 14:08:44 +00:00
44fee4e0eb
Remove several unused variables.
...
Patch by Alp Toker.
llvm-svn: 191757
2013-10-01 13:32:03 +00:00
6e96ac600f
[SystemZ] Allow integer OR involving high words
...
llvm-svn: 191755
2013-10-01 13:22:41 +00:00
1a56931b22
[SystemZ] Allow integer insertions with a high-word destination
...
llvm-svn: 191753
2013-10-01 13:18:56 +00:00
7c5c0eabc9
[SystemZ] Allow selects with a high-word destination
...
llvm-svn: 191751
2013-10-01 13:10:16 +00:00
012402346f
[SystemZ] Add patterns to load a constant into a high word (IIHF)
...
Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.
llvm-svn: 191750
2013-10-01 13:02:28 +00:00
510de640c3
[ARM] Remove an unused function from the disassembler.
...
Pointed out by Joerg.
llvm-svn: 191749
2013-10-01 13:01:10 +00:00
6de62d3966
Test commit. Updated comment.
...
llvm-svn: 191748
2013-10-01 12:53:00 +00:00
21235a256f
[SystemZ] Add register zero extensions involving at least one high word
...
llvm-svn: 191746
2013-10-01 12:49:07 +00:00
ad98f1671d
[ARM] Introduce the 'sevl' instruction in ARMv8.
...
This also removes the restriction on the immediate field of the 'hint'
instruction.
llvm-svn: 191744
2013-10-01 12:39:11 +00:00
5469c39a26
[SystemZ] Add truncating high-word stores (STCH and STHH)
...
llvm-svn: 191743
2013-10-01 12:22:49 +00:00
0d46b1a30f
[SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
...
llvm-svn: 191742
2013-10-01 12:19:08 +00:00
58f1ced564
SCEVExpander: Fix a regression I introduced by to eagerly adding RAII objects.
...
PR17425.
llvm-svn: 191741
2013-10-01 12:17:11 +00:00
89e160d975
[SystemZ] Add sign-extending high-word loads (LBH and LHH)
...
llvm-svn: 191740
2013-10-01 12:11:47 +00:00
0755c93b0c
[SystemZ] Use upper words of GR64s for codegen
...
This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store). The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.
The easiest way of testing this seemed to be add a new "h" register
constraint for high words. I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.
llvm-svn: 191739
2013-10-01 11:26:28 +00:00
a26a4b4f60
[SystemZ] Reapply: Add definitions of LFH and STFH
...
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts. That should have been fixed by r191735.
llvm-svn: 191738
2013-10-01 10:31:04 +00:00
0210dd4b93
[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
...
llvm-svn: 191737
2013-10-01 10:22:35 +00:00
2b953d0b39
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
...
llvm-svn: 191734
2013-10-01 09:48:56 +00:00
3b75f5d282
AVX-512: Added X86vzmovl patterns
...
llvm-svn: 191733
2013-10-01 08:38:02 +00:00
766c934814
Remove 0 as a valid encoding for the m-mmmm field.
...
llvm-svn: 191732
2013-10-01 07:10:28 +00:00
8b278c5dc4
Remove unneeded fields from disassembler internal instruction format.
...
llvm-svn: 191731
2013-10-01 06:56:57 +00:00
3bf0317fec
BEXTR should be defined to take same type for bother operands.
...
llvm-svn: 191728
2013-10-01 03:48:26 +00:00
6aada32dc4
SelectionDAG: Clarify comments from r191600
...
llvm-svn: 191724
2013-10-01 02:09:00 +00:00
ea395924d2
Adding multiple module support for MCJIT.
...
Tests to follow.
PIC with small code model and EH frame handling will not work with multiple modules. There are also some rough edges to be smoothed out for remote target support.
llvm-svn: 191722
2013-10-01 01:47:35 +00:00
9a08f9e561
Add the DW_AT_GNU_ranges_base attribute if we've emitted any ranges
...
into the debug_ranges section.
llvm-svn: 191721
2013-10-01 00:43:36 +00:00
1d06eb5d86
Update comments.
...
llvm-svn: 191720
2013-10-01 00:43:31 +00:00
5ea37f8d89
Fix code duplication
...
llvm-svn: 191716
2013-10-01 00:01:14 +00:00
f03a6e7fba
Forgot to add a break statement.
...
llvm-svn: 191715
2013-09-30 23:51:22 +00:00
a90a340fbb
Reuse variable
...
llvm-svn: 191712
2013-09-30 23:31:50 +00:00
f0b6288cbf
The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddress
...
on ADD16rr opcodes, if src1 != src, since that would cause
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.
This patch fixes PR16785.
llvm-svn: 191711
2013-09-30 23:18:42 +00:00
39eebfada6
The DW_AT_GNU_pubnames/pubtypes attributes are actually form
...
SEC_OFFSET from the beginning of the section so go ahead and emit
a label at the beginning of each one.
llvm-svn: 191710
2013-09-30 23:14:16 +00:00
27e783e90d
Fix getOrInsertGlobal dropping the address space.
...
Currently it will insert an illegal bitcast.
Arguably, the address space argument should be
added for the creation case.
llvm-svn: 191702
2013-09-30 21:23:03 +00:00
8468062c6e
Use right address space size in InstCombineCompares
...
The test's output doesn't change, but this ensures
this is actually hit with a different address space.
llvm-svn: 191701
2013-09-30 21:11:01 +00:00
06adecabe7
Constant fold ptrtoint + compare with address spaces
...
llvm-svn: 191699
2013-09-30 21:06:18 +00:00
aad5c3b81b
Debug Info: constify and rename from generateRef to getRef.
...
No functionality change.
llvm-svn: 191696
2013-09-30 19:42:10 +00:00
9515b31096
llvm-c: use typedef for function pointers
...
This makes it consistent with other function pointers used in llvm-c
Differential Revision: http://llvm-reviews.chandlerc.com/D1712
llvm-svn: 191693
2013-09-30 19:11:32 +00:00
8ff70e3e26
[mips][msa] Direct Object Emission for I8 instructions.
...
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.
Patch by Matheus Almeida
llvm-svn: 191688
2013-09-30 18:05:18 +00:00
c3b25686b9
[mips][msa] Direct Object Emission for I5 instructions.
...
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
llvm-svn: 191687
2013-09-30 17:58:07 +00:00
be904775d2
[ARM] Clean up ARMAsmParser::validateInstruction().
...
Fix some LLVM Coding Standards violations.
No changes in functionality.
llvm-svn: 191686
2013-09-30 17:57:30 +00:00
92e6e0f171
[mips][msa] Direct Object Emission for 2R instructions.
...
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.
Patch by Matheus Almeida
llvm-svn: 191685
2013-09-30 17:52:33 +00:00
6eed9cc6a8
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
...
and not an MSA register
Patch by Matheus Almeida
llvm-svn: 191684
2013-09-30 17:43:04 +00:00
Richard Sandiford