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11298 Commits

Author SHA1 Message Date
Owen Anderson b101af04b4 Convert this test to a .s file, so that it's not sensitive to codegen changes. 
llvm-svn: 117633
 2010-10-29 01:01:56 +00:00
Dan Gohman c16d9afe04 Add a basic testcase for TBAA-aware DSE. 
llvm-svn: 117632
 2010-10-29 00:54:02 +00:00
Chris Lattner 5d6f6a061b add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Andrew Trick fc1b990b1d The ARM jit cannot handle these tests as of 2010-10-27. 
(A PR will be linked to this rev.)

llvm-svn: 117620
 2010-10-29 00:23:43 +00:00
Rafael Espindola 8aefb66376 Improvements to .section parsing: 
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G

We ignore the G arguments and flag for now.

llvm-svn: 117608
 2010-10-28 21:33:33 +00:00
Chris Lattner 327a61423b most simple arm instructions match correctly now, 
it looks like we're not handling [] operands though

llvm-svn: 117607
 2010-10-28 21:31:07 +00:00
Chris Lattner 1be0697ab9 fix the asmmatcher generator to handle targets with no RegisterPrefix 
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
 2010-10-28 21:28:42 +00:00
Rafael Espindola 63760ba38e Add support for the .string directive. 
llvm-svn: 117592
 2010-10-28 20:02:27 +00:00
Rafael Espindola 3c5a54e4b9 Defined weak symbols should have non-zero value. 
llvm-svn: 117585
 2010-10-28 19:39:57 +00:00
Rafael Espindola 29f70afbae Fix relocations with renamed symbols. 
llvm-svn: 117575
 2010-10-28 19:08:03 +00:00
Rafael Espindola 6cd76e63f8 Aliases defined with .symver should copy the binding of the symbols they alias. 
Move the existing patching for undefined symbols so that all the patching
is done in the same function.

llvm-svn: 117570
 2010-10-28 18:33:03 +00:00
Bob Wilson f63da12be9 Teach the DAG combiner to fold a splat of a splat. Radar 8597790. 
Also do some minor refactoring to reduce indentation.

llvm-svn: 117558
 2010-10-28 17:06:14 +00:00
Roman Divacky fdac6365ab Implement .equ directive as a synonym to .set. 
llvm-svn: 117553
 2010-10-28 16:22:58 +00:00
Duncan Sands efb139130f Testcase for PR8494 (invalid bitcode crashing the bitcode reader). 
llvm-svn: 117552
 2010-10-28 15:57:30 +00:00
Rafael Espindola 936ba3af28 Implement R_X86_64_DTPOFF32. 
llvm-svn: 117548
 2010-10-28 15:11:03 +00:00
Rafael Espindola 2dbec3f762 Implement TLSLD. 
llvm-svn: 117547
 2010-10-28 15:02:40 +00:00
Rafael Espindola e8f08be11c Implement DTPOFF. 
llvm-svn: 117546
 2010-10-28 14:48:59 +00:00
Rafael Espindola 6f23eb380d Implement TLSLDM. 
llvm-svn: 117544
 2010-10-28 14:37:09 +00:00
Rafael Espindola b3b49bbc39 Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind. 
llvm-svn: 117543
 2010-10-28 14:22:44 +00:00
Evan Cheng ff310737e5 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng 0165e25564 Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful. 
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.

llvm-svn: 117530
 2010-10-28 06:46:17 +00:00
NAKAMURA Takumi 959807fa37 test/Transforms/SimplifyLibCalls/floor.ll: Mark as XFAIL:win32 due to lack of nearbyintf on MSVC. [PR8466] 
llvm-svn: 117529
 2010-10-28 06:46:04 +00:00
Evan Cheng e2c211c1b9 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng ff1c862f8e - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Dale Johannesen 9c3f6bf2bf Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
 2010-10-28 00:35:54 +00:00
Owen Anderson 2ef668840a Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00
Owen Anderson 14be930317 Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
llvm-svn: 117512
 2010-10-27 23:56:39 +00:00
Dale Johannesen 16bb87a90e Teach InstCombine not to use Add and Neg on FP. PR 8490. 
llvm-svn: 117510
 2010-10-27 23:45:18 +00:00
Evan Cheng 59bbc545e0 Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Owen Anderson 9f371e7efa Tests for NEON encoding of vrev. 
llvm-svn: 117502
 2010-10-27 22:54:49 +00:00
Owen Anderson fadb951e5b Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Owen Anderson ed9652f959 Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Rafael Espindola f8537165bd Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE. 
llvm-svn: 117494
 2010-10-27 21:23:52 +00:00
Kevin Enderby 5e7cb5fc27 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Bob Wilson c7334a146e SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
 2010-10-27 20:38:28 +00:00
Rafael Espindola 24c8b04d5f Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32. 
llvm-svn: 117481
 2010-10-27 20:28:07 +00:00
Owen Anderson 40d24a4abf Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Rafael Espindola 095fa9e5cc Set default type and flags for .init and .fini. 
llvm-svn: 117471
 2010-10-27 18:45:20 +00:00
Owen Anderson fbdeab911a Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun. 
llvm-svn: 117469
 2010-10-27 18:17:12 +00:00
Owen Anderson 5fa98baef7 Tests for NEON encoding of vcls, vclz, and vcnt. 
llvm-svn: 117466
 2010-10-27 18:05:25 +00:00
Owen Anderson 6b5af599c0 Tests for NEON encoding of vneg and vqneg. 
llvm-svn: 117463
 2010-10-27 17:57:26 +00:00
Rafael Espindola 26496e6835 Produce an error for an invalid use of .symver. 
llvm-svn: 117462
 2010-10-27 17:56:18 +00:00
Owen Anderson 1e5eb98ed8 Tests for NEON encoding of vabs and vqabs. 
llvm-svn: 117460
 2010-10-27 17:50:07 +00:00
Owen Anderson 8576a42cf3 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson d7e8135e1e Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Rafael Espindola cc1b168ef6 Symbols defined as the difference of other two end up in the ABS section. 
llvm-svn: 117451
 2010-10-27 16:04:30 +00:00
Rafael Espindola eb0c2c170d Add support for the .symver directive. This is really ugly, but most of it is 
contained in the ELF object writer.

llvm-svn: 117448
 2010-10-27 15:18:17 +00:00
Kevin Enderby 9ad2166899 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby 20b021c970 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby a1917c7555 Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00