2f8637d393
These don't need to be virtual.
...
llvm-svn: 117068
2010-10-21 21:47:51 +00:00
2bfa8ed045
Move the encoding logic for Q registers into getMachineOpValue().
...
llvm-svn: 117060
2010-10-21 20:49:13 +00:00
9e44cf2bb2
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
llvm-svn: 117056
2010-10-21 20:21:49 +00:00
b353e4f579
Handle storing args to the stack for calls.
...
llvm-svn: 117055
2010-10-21 20:09:54 +00:00
a7f6150c14
Adding initial AsmParser implementation for the MBlaze backend. It is
...
mostly based on the ARM AsmParser at this time and is not particularly
functional.
Changed the MBlaze data layout from:
"E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
"E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.
Cleaned up the MBlaze source code:
1. The floating point register class has been removed. The
MicroBlaze does not have floating point registers. Floating
point values are simply stored in integer registers.
2. Renaming the CPURegs register class to GPR to reflect the
standard naming.
3. Removing a lot of stale code from AsmPrinter after
the conversion to InstPrinter.
4. Simplified sign extended loads by marking them as
expanded in ISelLowering.
llvm-svn: 117054
2010-10-21 19:48:38 +00:00
73bc5b0f86
More load/store refactoring, call reg+offset simplification from within
...
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
llvm-svn: 117051
2010-10-21 19:40:30 +00:00
d37f0715b1
trailing whitespace
...
llvm-svn: 117050
2010-10-21 19:38:40 +00:00
6b7e401049
Add correct NEON encodings for vhadd and vrhadd.
...
llvm-svn: 117047
2010-10-21 18:55:04 +00:00
9561084188
Add correct encodings for NEON vaddw.s* and vaddw.u*.
...
llvm-svn: 117040
2010-10-21 18:20:25 +00:00
15c97706e8
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
...
llvm-svn: 117039
2010-10-21 18:09:17 +00:00
0138a05557
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
llvm-svn: 117031
2010-10-21 17:16:46 +00:00
b014abf3ef
The return value of this call is not used, so no point
...
in assigning it to a variable (gcc-4.6 warning).
llvm-svn: 117024
2010-10-21 16:06:28 +00:00
ee4eb2bad1
Remove some variables that are never really used
...
(gcc-4.6 warns about these).
llvm-svn: 117021
2010-10-21 16:03:28 +00:00
1f0d37e892
Add parentheses to pacify gcc, which warns otherwise.
...
llvm-svn: 117020
2010-10-21 16:02:12 +00:00
f7ecd9e8bb
Removing stale AsmPrinter directory from MicroBlaze backend.
...
llvm-svn: 116998
2010-10-21 05:05:06 +00:00
3e79a47a7a
Deleted lib/Target/MBlaze/AsmPrinter/CMakeLists.txt. This way the
...
CMake build does not try to build that library, which collides with
MBlaze/InstPrinter.
llvm-svn: 116997
2010-10-21 05:01:26 +00:00
c16f77fb27
Recommit 116986 with capitalization typo fixed.
...
llvm-svn: 116993
2010-10-21 03:57:26 +00:00
f4ebec03e0
putback r116983 and fix simple-fp-encoding.ll tests
...
llvm-svn: 116992
2010-10-21 03:40:16 +00:00
078db00f1d
Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it
...
compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.
llvm-svn: 116991
2010-10-21 03:34:22 +00:00
9e00f27e14
Revert r116983, which is breaking all the buildbots.
...
llvm-svn: 116987
2010-10-21 03:11:16 +00:00
f608ac4db9
Major update of the MicroBlaze backend. The new features are:
...
1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
llvm-svn: 116986
2010-10-21 03:09:55 +00:00
f509c6ca27
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.
...
llvm-svn: 116984
2010-10-21 01:41:01 +00:00
15c2ac90ec
Add missing scheduling itineraries for transfers between core registers and VFP registers.
...
llvm-svn: 116983
2010-10-21 01:12:00 +00:00
6083502848
Implement correct encodings for NEON vadd, both integer and floating point.
...
llvm-svn: 116981
2010-10-21 00:48:00 +00:00
83ce5f181f
CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args.
...
This should be the minimum set of functions that could possibly need it.
llvm-svn: 116978
2010-10-21 00:08:21 +00:00
4ac3ed0219
Custom lower f64 args passed in integer registers.
...
llvm-svn: 116977
2010-10-21 00:01:47 +00:00
9cafc872ab
Fix Whitespace.
...
llvm-svn: 116972
2010-10-20 23:40:27 +00:00
a65f914bb0
Add encoding for moving a value between two ARM core registers and a doublework
...
extension register.
llvm-svn: 116970
2010-10-20 23:37:40 +00:00
058190507b
Add encodings for movement between ARM core registers and single-precision
...
registers.
llvm-svn: 116961
2010-10-20 22:44:54 +00:00
ff37675c72
Fix crash introduced in 116852. 8573915.
...
llvm-svn: 116955
2010-10-20 22:03:37 +00:00
320a553319
Remove Synthesizable from the Type system; as MMX vector
...
types are no longer Legal on X86, we don't need it.
No functional change. 8499854.
llvm-svn: 116947
2010-10-20 21:32:10 +00:00
89f6613e76
Handle _GLOBAL_OFFSET_TABLE_ correctly.
...
llvm-svn: 116932
2010-10-20 16:46:08 +00:00
1898262a33
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
...
#includes in the process.
llvm-svn: 116919
2010-10-20 08:27:02 +00:00
af719ef86b
Fix a TODO by removing some unnecesary copies.
...
llvm-svn: 116915
2010-10-20 08:02:24 +00:00
723159ef77
Fix backwards conditional.
...
llvm-svn: 116897
2010-10-20 01:10:01 +00:00
cb6fc2b2de
Add dynamic realignment when rematerializing the base register.
...
llvm-svn: 116886
2010-10-20 00:02:50 +00:00
f99ee7cd91
Nuke a commented out bit that got missed a while back.
...
llvm-svn: 116883
2010-10-19 23:48:47 +00:00
bbdc5d2ef9
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
...
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
llvm-svn: 116879
2010-10-19 23:27:08 +00:00
3ed6338ff2
Update comments to remove obsolete references.
...
llvm-svn: 116863
2010-10-19 21:34:47 +00:00
710a2d9d46
Enable using vdup for vector constants which are splat of
...
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
llvm-svn: 116852
2010-10-19 20:00:17 +00:00
63c7608c34
Re-enable register pressure aware machine licm with fixes. Hoist() may have
...
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
llvm-svn: 116845
2010-10-19 18:58:51 +00:00
6c18d1aac0
Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which
...
must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize
the pass's dependencies.
Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.
I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems
with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass
registration/creation, please send the testcase to me directly.
llvm-svn: 116820
2010-10-19 17:21:58 +00:00
418204e523
Revert r116781 "- Add a hook for target to determine whether an instruction def
...
is", which breaks some nightly tests.
llvm-svn: 116816
2010-10-19 17:14:24 +00:00
05046a177d
Add lower argument and return of device function
...
llvm-svn: 116805
2010-10-19 13:14:40 +00:00
3e64de9504
X86: Add MS-CRT libcalls.
...
llvm-svn: 116801
2010-10-19 07:32:52 +00:00
8b382e7e10
Fix Whitespace.
...
llvm-svn: 116800
2010-10-19 07:32:42 +00:00
8249dfe6ce
- Add a hook for target to determine whether an instruction def is
...
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
llvm-svn: 116781
2010-10-19 00:55:07 +00:00
b6d61dc291
Support alignment for NEON vld-lane and vst-lane instructions.
...
llvm-svn: 116776
2010-10-19 00:16:32 +00:00
49843c0162
Added a few tweaks to the Intel Descriptor-table support instructions to allow
...
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
llvm-svn: 116773
2010-10-19 00:01:44 +00:00
1c6fd774f7
ARM encoding information for [SU]SAT* instructions.
...
llvm-svn: 116768
2010-10-18 23:35:38 +00:00
7b92c2a9a0
Revert r116220 - thus turning arm fast isel back on by default.
...
llvm-svn: 116762
2010-10-18 22:53:53 +00:00
337a31133b
Don't recompute MachineRegisterInfo in the Optimize* method.
...
llvm-svn: 116750
2010-10-18 21:22:31 +00:00
6706f3c4b4
For Thumb2, try to use frame pointer references for stack slots even when a
...
base register is available. rdar://8525298
llvm-svn: 116729
2010-10-18 18:39:46 +00:00
e3dc9e2ea1
Produce ELF::R_386_GOTPC relocations.
...
llvm-svn: 116728
2010-10-18 18:36:12 +00:00
b9783dd9bc
Added a handful of x86-32 instructions that were missing so that llvm-mc would
...
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
llvm-svn: 116716
2010-10-18 17:04:36 +00:00
00fe92da6b
ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
...
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625
llvm-svn: 116714
2010-10-18 16:48:59 +00:00
e8a0eaafe6
Grammar tweak.
...
llvm-svn: 116712
2010-10-18 16:38:50 +00:00
5f2034c455
Improve lowering of sext to i128 on SPU.
...
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.
llvm-svn: 116701
2010-10-18 09:34:19 +00:00
167a700229
Remove the check for invalid calling conventions. Testing shows that they're
...
working just fine.
llvm-svn: 116698
2010-10-18 06:49:12 +00:00
c103c668ce
Lift arg promotion from the X86 backend. This should be unified at some point.
...
llvm-svn: 116694
2010-10-18 02:17:53 +00:00
a8a9f3c52b
Now that we handle all allocas via a non-SP reg offset remove all of the
...
special case handling for ARM::SP.
llvm-svn: 116688
2010-10-17 11:08:44 +00:00
730764da62
Allow more load types to be materialized through the allocas.
...
llvm-svn: 116683
2010-10-17 06:07:26 +00:00
d265b3fcfe
Optimize GEP off of intermediate allocas.
...
llvm-svn: 116681
2010-10-17 01:51:42 +00:00
a0b9c2e9c0
Fix comment.
...
llvm-svn: 116680
2010-10-17 01:42:53 +00:00
abc3a9d34b
Turn on AddOperator folding in GEP.
...
llvm-svn: 116679
2010-10-17 01:41:46 +00:00
947e422c46
Use the i12 immediate versions of the load instructions - they're handled
...
more in the post-passes.
llvm-svn: 116678
2010-10-17 01:40:27 +00:00
4262a22225
Add a MCObjectFormat class so that code common to all targets that use a
...
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
5e683250ee
X86-Windows: Emit an undefined global __fltused symbol when targeting Windows
...
if any floating point arguments are passed to an external function.
llvm-svn: 116665
2010-10-16 08:25:41 +00:00
c918d550b6
Fix some funky formatting that got through.
...
llvm-svn: 116653
2010-10-16 01:10:35 +00:00
5f5b922ec6
ARMCodeEmitter::emitMiscInstruction is dead. Long live
...
ARMCodeEmitter::emitMiscInstruction!
llvm-svn: 116644
2010-10-15 23:35:12 +00:00
f410acbbd5
Make sure offset is 0 for load/store register to the stack call.
...
llvm-svn: 116640
2010-10-15 23:07:10 +00:00
d2466687bf
Formatting.
...
llvm-svn: 116635
2010-10-15 22:49:28 +00:00
a3e64c1791
Fix else if -> if in store machinery.
...
llvm-svn: 116628
2010-10-15 22:32:37 +00:00
399add01d4
Reformatting. No functionalogicality changes.
...
llvm-svn: 116625
2010-10-15 21:50:45 +00:00
a9b3901b47
Refactor ARM fast-isel reg + offset to be a base + offset.
...
llvm-svn: 116622
2010-10-15 21:32:12 +00:00
90f74fe16a
Encoding information for the various ARM saturating add/sub instructions.
...
llvm-svn: 116612
2010-10-15 19:49:46 +00:00
00ce8deae6
ARM binary encoding information for RSB and RSC instructions.
...
llvm-svn: 116604
2010-10-15 18:42:41 +00:00
2d00b1b2e5
Don't mark argument value stores as immutable, as otherwise the post-RA
...
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer
llvm-svn: 116602
2010-10-15 18:34:47 +00:00
f1b3681ed0
Use simple RegState::Define flag instead of getDefRegState(true).
...
llvm-svn: 116601
2010-10-15 18:25:59 +00:00
e4b3d6b379
Expand GEP handling for constant offsets.
...
llvm-svn: 116594
2010-10-15 18:02:07 +00:00
d15723c22a
When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
...
an explicit def. Make sure to capture that properly. rdar://8556556
llvm-svn: 116591
2010-10-15 17:35:17 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
3b1db392fc
Remove unused ARMISD::AND selection DAG node.
...
llvm-svn: 116566
2010-10-15 04:34:40 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
118c4238ff
Encoding info for extension instructions.
...
llvm-svn: 116560
2010-10-15 02:29:58 +00:00
19c6cb978b
Add missing Rd encoding for MOVs instruction.
...
llvm-svn: 116537
2010-10-14 23:28:31 +00:00
8b6a9c1574
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
...
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
062749cb25
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
eafcb27ded
MOVi16 and MOVT ARM mode encodings.
...
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
8229153629
Simplify encoding information and add 'dst' operand info for TAILJMP.
...
llvm-svn: 116488
2010-10-14 17:24:28 +00:00
5816ccd4b5
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
...
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
llvm-svn: 116480
2010-10-14 15:54:46 +00:00
21d0c173f4
Handle more complex GEP based loads and add a few TODOs to deal with
...
GEP + alloca.
llvm-svn: 116474
2010-10-14 09:29:41 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
...
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
0441c6cba0
Add encoding for 'fmstat'.
...
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
0825f3e441
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
1f2b4bdb22
Regenerate. No functional change, just cleanup.
...
llvm-svn: 116459
2010-10-14 00:15:18 +00:00
d100ed858e
Detabify and clean up 80 column violations.
...
llvm-svn: 116454
2010-10-13 23:47:11 +00:00
340cd5174b
A few 80 column fixes.
...
llvm-svn: 116451
2010-10-13 23:34:31 +00:00
b9386558a7
trailing whitespace
...
llvm-svn: 116450
2010-10-13 23:12:26 +00:00
348013f829
Add a FIXME.
...
llvm-svn: 116449
2010-10-13 22:55:33 +00:00
0708e74a95
Add operand encoding bits for SMC and SVC in ARM mode.
...
llvm-svn: 116447
2010-10-13 22:38:23 +00:00
16db3287c0
More encoding cleanup. Also add register Rd operands for indirect branches.
...
llvm-svn: 116444
2010-10-13 22:09:34 +00:00
2a4d99ab62
Simplify some ARM encoding information.
...
llvm-svn: 116440
2010-10-13 21:48:54 +00:00
ef83e21b57
Update comment.
...
llvm-svn: 116438
2010-10-13 21:41:51 +00:00
9874b7de58
Add a FIXME. The ADR instruction is a bit odd.
...
llvm-svn: 116437
2010-10-13 21:32:30 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
fb07ef19cc
Add a FIXME.
...
llvm-svn: 116428
2010-10-13 20:38:04 +00:00
efc066829b
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
...
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
llvm-svn: 116427
2010-10-13 20:30:55 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
142e3cbb26
Fix encoding for compares. No Rd register.
...
llvm-svn: 116414
2010-10-13 18:05:25 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
...
immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
...
8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
dd0821e7ff
Start handling more global variables.
...
llvm-svn: 116401
2010-10-13 09:11:46 +00:00
3912158997
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
...
llvm-svn: 116389
2010-10-13 01:54:21 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
f9ca535495
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
efd5369749
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
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llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
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llvm-svn: 116370
2010-10-12 23:22:27 +00:00
d565b44a98
Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.
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llvm-svn: 116368
2010-10-12 23:19:28 +00:00
12e493ace4
Move the ARM so_imm encoding into a custom operand encoder and remove the
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explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
42200bcaea
Refactor some of the encoding logic into a base class. This keeps us from having
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to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
llvm-svn: 116362
2010-10-12 23:06:54 +00:00
d9d31dafda
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
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instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
646a506724
Add encoding for VSUB and VCMP.
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Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
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llvm-svn: 116348
2010-10-12 22:08:41 +00:00
98c29d732d
Split out the "size" field from the encoding. The newer documentation has it as
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a separate bit in the coding.
llvm-svn: 116347
2010-10-12 22:03:19 +00:00
22e051eef0
Fix thinko in arm fast isel alloca rewrite.
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llvm-svn: 116339
2010-10-12 21:23:43 +00:00
576640f0e3
Encoding for ARM-mode VADD.F32 instruction.
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llvm-svn: 116338
2010-10-12 21:22:40 +00:00
604e142844
Combine these together - should probably have some text associated
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that says what why what we just asserted is wrong.
llvm-svn: 116333
2010-10-12 19:44:17 +00:00
eb7b91d417
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
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llvm-svn: 116323
2010-10-12 18:18:03 +00:00
0e57a9f7a9
Add MOVi ARM encoding.
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llvm-svn: 116321
2010-10-12 18:09:12 +00:00
395a898b2b
Initial va_arg support for x86-64. Patch by David Meyer!
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llvm-svn: 116319
2010-10-12 18:00:49 +00:00
feeae27ad9
Nuke unused wrapper function.
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llvm-svn: 116318
2010-10-12 17:53:25 +00:00
aec745326a
Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
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The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.
The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.
llvm-svn: 116314
2010-10-12 17:15:00 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
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ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
dd6eb5b5a1
PR8359: The ARM backend may end up allocating registers D16 to D31 when
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"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
7cd5cda6bb
Rework alloca handling so that we can load or store from casted
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address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
db3bcc9910
Handle a wider arrangement of loads.
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llvm-svn: 116284
2010-10-12 00:43:21 +00:00
e790afcbe1
More ARM scheduling itinerary fixes.
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llvm-svn: 116266
2010-10-11 23:41:41 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
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register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
109ff296c8
Second set of ARM/MC/ELF changes.
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Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
94ad008beb
Proper VST scheduling itineraries.
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llvm-svn: 116251
2010-10-11 22:03:18 +00:00
d42340ecfd
Use a sane mechanism for that assert.
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llvm-svn: 116249
2010-10-11 22:01:22 +00:00
72b91c1765
We're not going to handle dynamic allocas anywhere else.
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llvm-svn: 116240
2010-10-11 21:37:35 +00:00
71ef1af66b
Make sure that the call stack adjustments have default operands. Also
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leave custom lowerings for later.
Fixes some nightly tests.
llvm-svn: 116232
2010-10-11 21:20:02 +00:00
Eric Christopher