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639 Commits

Author SHA1 Message Date
Nate Begeman 8a0933608a First round of support for doing scalar FP using the SSE2 ISA extension and 
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
 2005-07-06 18:59:04 +00:00
Misha Brukman c88330ad13 * Remove trailing whitespace 
* Convert tabs to spaces

llvm-svn: 21426
 2005-04-21 23:38:14 +00:00
Chris Lattner 25be208e02 When commuting these instructions, make sure to actually swap the operands too. 
llvm-svn: 19694
 2005-01-19 16:55:52 +00:00
Chris Lattner d54845f530 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. 
llvm-svn: 19687
 2005-01-19 07:31:24 +00:00
Chris Lattner 2947801735 Teach the code generator that shrd/shld is commutable if it has an immediate. 
This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.

llvm-svn: 19686
 2005-01-19 07:11:01 +00:00
Chris Lattner 733aac1270 Disable 2->3 address promotion of add and inc instructions to LEA's. In 
addition to being three address, LEA's don't set the flags.

This fixes 186.crafty.

llvm-svn: 19251
 2005-01-02 04:18:17 +00:00
Chris Lattner b7782d77c1 Implement the convertToThreeAddress method, add support for inverting JP/JNP 
branches.

llvm-svn: 19247
 2005-01-02 02:37:07 +00:00
Chris Lattner 4d7af1c680 Fix a warning 
llvm-svn: 15409
 2004-08-01 19:31:30 +00:00
Alkis Evlogimenos bb635a27a4 Align breaks. 
llvm-svn: 15371
 2004-07-31 10:05:44 +00:00
Chris Lattner fcef7655fa Add breaks 
llvm-svn: 15365
 2004-07-31 09:53:31 +00:00
Alkis Evlogimenos ce15f8f4c9 Simplify code a bit. 
llvm-svn: 15364
 2004-07-31 09:44:32 +00:00
Alkis Evlogimenos aaf642103a Correctly spell 'unconditional'. 
llvm-svn: 15363
 2004-07-31 09:41:44 +00:00
Alkis Evlogimenos f57d78a87d Implement insertGoto and reverseBranchCondition for the X86. 
llvm-svn: 15362
 2004-07-31 09:38:47 +00:00
Alkis Evlogimenos ea81b79a97 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
 2004-02-29 08:50:03 +00:00
Chris Lattner ed01da8f0b Adjust to change in TII ctor arguments 
llvm-svn: 11987
 2004-02-29 06:31:44 +00:00
Chris Lattner ca89812db7 These two virtual methods are never called. 
llvm-svn: 11984
 2004-02-29 05:59:33 +00:00
Alkis Evlogimenos 8358cc573d Move MOTy::UseType enum into MachineOperand. This eliminates the 
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).

llvm-svn: 11715
 2004-02-22 19:23:26 +00:00
Alkis Evlogimenos 8cdd0215bf Remove getAllocatedRegNum(). Use getReg() instead. 
llvm-svn: 11393
 2004-02-13 21:01:20 +00:00
Chris Lattner 92252f42c3 Don't use MachineOperator::is(Phys|Virt)Register 
llvm-svn: 11276
 2004-02-10 20:31:28 +00:00
Chris Lattner 259e98ed27 Tighten up checks 
llvm-svn: 11274
 2004-02-10 20:25:13 +00:00
Alkis Evlogimenos aeb8a80c71 FpMOV is also a move instruction. 
llvm-svn: 11055
 2004-02-01 08:22:16 +00:00
Alkis Evlogimenos 52564b2071 Add TargetInstrInfo::isMoveInstr() to support coalescing in register 
allocation.

llvm-svn: 10633
 2003-12-28 17:35:08 +00:00
Brian Gaeke 960707c335 Put all LLVM code into the llvm namespace, as per bug 109. 
llvm-svn: 9903
 2003-11-11 22:41:34 +00:00
John Criswell 482202a601 Added LLVM project notice to the top of every C++ source file. 
Header files will be on the way.

llvm-svn: 9298
 2003-10-20 19:43:21 +00:00
Chris Lattner 05e2f385a7 * Start using tablegen'd instruction descriptions 
* Fix bug in the createNOP method, which was not marking the operands of the
  generated XCHG as useanddef.  I don't think this method is actually used,
  so it wasn't breaking anything, but it should be fixed anyway...

llvm-svn: 7539
 2003-08-03 21:55:55 +00:00
Misha Brukman e2402c65d0 Reword to remove reference to how things worked in the past. 
llvm-svn: 6323
 2003-05-24 01:08:43 +00:00
Misha Brukman d21a02ad58 Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface. 
llvm-svn: 6320
 2003-05-24 00:09:50 +00:00
Chris Lattner b4d58d7f9e Rename MachineInstrInfo -> TargetInstrInfo 
llvm-svn: 5272
 2003-01-14 22:00:31 +00:00
Chris Lattner b54343a64f Add comments, switch uses/defs to match InstrInfo.def file 
llvm-svn: 5102
 2002-12-18 01:05:54 +00:00
Chris Lattner 0d80874f6c * Move information about Implicit Defs/Uses into X86InstrInfo.def. 
* Expose information about implicit defs/uses of register through the
  MachineInstrInfo.h file.

llvm-svn: 4877
 2002-12-03 05:42:53 +00:00
Misha Brukman 1a72c637fb Added -*- C++ -*- mode to the comments. 
llvm-svn: 4826
 2002-11-22 22:42:50 +00:00
Chris Lattner cf72e52df3 Expose base opcode 
llvm-svn: 4742
 2002-11-18 06:56:24 +00:00
Chris Lattner 0018e8d5fc Start to add more information to instr.def 
llvm-svn: 4741
 2002-11-18 05:37:11 +00:00
Chris Lattner 9289d7d693 Reorganize printing interface a bit 
llvm-svn: 4728
 2002-11-17 22:53:13 +00:00
Chris Lattner 87b84a6913 Set the destination register field based on the target specific flags 
llvm-svn: 4442
 2002-10-30 01:15:31 +00:00
Chris Lattner 27d247978b Rename X86InstructionInfo to X86InstrInfo 
llvm-svn: 4413
 2002-10-29 21:05:24 +00:00
Chris Lattner f57420ee17 Minor renaming 
llvm-svn: 4410
 2002-10-29 20:48:56 +00:00
Chris Lattner 16cbd41c21 Implement MachineInstrInfo interface 
llvm-svn: 4394
 2002-10-29 17:43:19 +00:00
Chris Lattner d92fb0058b Initial checkin of X86 backend. 
We can instruction select exactly one instruction 'ret void'.  Wow.

llvm-svn: 4284
 2002-10-25 22:55:53 +00:00