Commit Graph

370552 Commits

Author SHA1 Message Date
Jonas Devlieghere 30e7df0d58 [lldb] XFAIL TestTypeGetModule.py (temporarily)
Temporarily XFAIL'ing TestTypeGetModule.py while the DWO failure is
being investigated.
2020-10-29 18:37:46 -07:00
Ilya Bukonkin 56282cf7e2 [lldb] Update TestTypeGetModule.py
Differential revision: https://reviews.llvm.org/D88483
2020-10-29 18:28:57 -07:00
Arthur Eubanks d673beee55 [PruneEH] Pin tests to legacy PM
prune-eh will not be ported to the NPM. Instead, a combination of
function-attrs and simplifycfg should be used (as described in
https://reviews.llvm.org/D44415).

This pins most tests using -prune-eh to the legacy PM. Some of these
were testing legacy PM infra (mostly the CGPassManager). Some of these
can be tested in the NPM using function-attrs and simplifycfg.

One interesting case is simplenoreturntest.ll. function-attrs +
simplifycfg does not yet make a caller of a caller of a noreturn
function end with unreachable like prune-eh does. That can be added in
the future.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D90012
2020-10-29 18:17:55 -07:00
Alina Sbirlea 9d93b150c9 [AA] Pass query info.
Pass AAQI in places where it was missed.

Part of D89991.
Author: haoranxu510 (Haoran Xu)
2020-10-29 18:07:53 -07:00
Jonas Devlieghere db3dba52ca [dwarfdump] Recognize __apple sections as debug info sections
Recognize the __apple_ sections as debug info sections and make sure
they're included in the --show-sections-sizes output.

Differential revision: https://reviews.llvm.org/D90433
2020-10-29 17:54:34 -07:00
Keith Smiley 29f9db7125 [llvm-readobj][NFC] Remove unused prefix from FileCheck tests
This is to enable --allow-unused-duplicates=false. This prefix appears
to be outdated and intentionally unused.

Reviewed By: rupprecht

Differential Revision: https://reviews.llvm.org/D90427
2020-10-29 17:54:01 -07:00
Stella Laurenzo c645ea5e29 Add InsertionPoint and context managers to the Python API.
* Removes index based insertion. All insertion now happens through the insertion point.
* Introduces thread local context managers for implicit creation relative to an insertion point.
* Introduces (but does not yet use) binding the Context to the thread local context stack. Intent is to refactor all methods to take context optionally and have them use the default if available.
* Adds C APIs for mlirOperationGetParentOperation(), mlirOperationGetBlock() and mlirBlockGetTerminator().
* Removes an assert in PyOperation creation that was incorrectly constraining. There is already a TODO to rework the keepAlive field that it was guarding and without the assert, it is no worse than the current state.

Differential Revision: https://reviews.llvm.org/D90368
2020-10-29 17:50:13 -07:00
Wouter van Oortmerssen b8c2d60df5 [WebAssembly] Improved LLD error messages in case of mixed wasm32/wasm64 object files
Differential Revision: https://reviews.llvm.org/D90428
2020-10-29 17:15:59 -07:00
Nico Weber f1e0944fe5 clang-tidy: Make tests more hermetic
Make check_clang_tidy.py not just pass -format-style=none by default
but a full -config={}. Without this, with a build dir outside of
the llvm root dir and a .clang-tidy config further up that contains

  CheckOptions:
    - key:          modernize-use-default-member-init.UseAssignment
      value:        1

these tests would fail:

   Clang Tools :: clang-tidy/checkers/cppcoreguidelines-prefer-member-initializer-modernize-use-default-member-init.cpp
   Clang Tools :: clang-tidy/checkers/modernize-use-default-member-init-bitfield.cpp
   Clang Tools :: clang-tidy/checkers/modernize-use-default-member-init.cpp

After this change, they pass fine, despite the unrelated
.clang-tidy file further up.
2020-10-29 20:14:57 -04:00
Krzysztof Parzyszek db60e64036 [Hexagon] Handle additional shuffles that can be made perfect 2020-10-29 19:09:00 -05:00
Jim Ingham 32a85b268a This is a preliminary version of the test for https://reviews.llvm.org/D88483.
The test can be cleaned up a bit, but this should be good to see why the
Debian bot is failing...
2020-10-29 16:39:35 -07:00
Aaron Puchert bbed8cfe80 Thread safety analysis: Consider static class members as inaccessible
This fixes the issue pointed out in D84604#2363134. For now we exclude
static members completely, we'll take them into account later.
2020-10-30 00:35:14 +01:00
Arthur Eubanks 99f2779c18 [NFC] Fix typo function -> module 2020-10-29 16:10:56 -07:00
Scott Linder 580f99bcff [NFC][AMDGPU] Resize Memory Model columns in AMDGPUUsage.rst
Make all of the "AMDGPU Machine Code GFX*" columns in the Memory Model
table a consistent width of 32-characters.

Best viewed with something like --word-diff

Differential Revision: https://reviews.llvm.org/D89977
2020-10-29 23:07:03 +00:00
Scott Linder fb37943cc8 [AMDGPU] Update Memory Model in AMDGPUUsage.rst
Mostly NFC, but some changes are "bug fixes" rather than just e.g.
formatting changes or typo corrections.

- Fix typo "competing" -> "completing".
- Document why waintcnt is added to stores and not loads for
  sequentially consistent ordering.
- Lowercase some mentions of `buffer_gl{0,1}_inv`.
- Make mentions of `*cnt(0)` consistently include the `(0)` count.
- Remove some mentions of instructions for incorrect address spaces. For
  example, remove mention of `flat_load` from
  `load atomic acquire workgroup global`.
- Re-flow some text to get all the target columns to fit in a
  32-character wide column. Makes a future NFC patch to make these columns
  both 32-character wide more straightforward.

Modified cherry-pick of patch by Tony Tye

Reviewed By: t-tye

Differential Revision: https://reviews.llvm.org/D89596
2020-10-29 23:07:03 +00:00
Kostya Kortchinsky 3591721ada [GWP-ASan] Add mutexes for Fuchsia
Mitch expressed a preference to not have `#ifdef`s in platform agnostic
code, this change tries to accomodate this.

I am not attached to the method this CL proposes, so if anyone has a
suggestion, I am open.

We move the platform specific member of the mutex into its own platform
specific class that the main `Mutex` class inherits from. Functions are
implemented in their respective platform specific compilation units.

For Fuchsia, we use the sync APIs, as those are also the ones being
used in Scudo.

Differential Revision: https://reviews.llvm.org/D90351
2020-10-29 15:51:13 -07:00
Joachim Meyer eaee608448 [OpenMP] Use __OPENMP_NVPTX__ instead of _OPENMP in complex wrapper headers.
This is very similar to 7f1e6fcff9, just fixing a left-over.
With this, it should be possible to use both, -x cuda and -fopenmp in the same invocation,
enabling to use both OpenMP, targeting CPU, and CUDA, targeting the GPU.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D90415
2020-10-29 23:24:49 +01:00
Jim Ingham fa5a132767 Provide a reasonable value for PATH_MAX if the lldb headers don't provide it. 2020-10-29 15:02:51 -07:00
Thomas Raoux 5d45f758f0 [mlir][vector] Improve vector distribute integration test and fix block distribution
Fix semantic in the distribute integration test based on offline feedback. This
exposed a bug in block distribution, we need to make sure the id is multiplied
by the stride of the vector. Fix the transformation and unit test.

Differential Revision: https://reviews.llvm.org/D89291
2020-10-29 14:54:53 -07:00
Craig Topper 74b078294f [RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW
This combine makes two calls to SimplifyDemandedBits, one for the LHS and one
for the RHS. If the LHS call returns true, we don't make the RHS call. When
SimplifyDemandedBits makes a change, it will add the nodes around the change to
the DAG combiner worklist. If the simplification happens on the first recursion
step, the N will get added to the worklist. But if the simplification happens
deeper in the recursion, then N will not be revisited until the next time the
DAG combiner runs.

This patch explicitly addes N to the worklist anytime a Simplification is made.
Without this we might miss additional simplifications on the LHS or never
simplify the RHS. Special care also needs to be taken to not add N if it has
been CSEd by the simplification. There are similar examples in DAGCombiner and
the X86 target, but I don't have a test for it for RISC-V. I've also returned
SDValue(N, 0) instead of SDValue() so DAGCombiner knows a change was made and
will update its Statistic variable.

The test here was constructed so that 2 simplifications happen to the LHS.
Without this fix one happens in the post type legalization DAG combine and the
other happens after LegalizeDAG. This prevents the RHS from ever being
simplified causing the left and right shift to clear the upper 32 bits of the
RHS to be left behind.

Differential Revision: https://reviews.llvm.org/D90339
2020-10-29 14:52:53 -07:00
Craig Topper 541effe082 [RISCV] Add test case for D90339 2020-10-29 14:52:24 -07:00
Jim Ingham c8c07b76b2 Use !hasLocalLinkage instead of listing the symbol types
we should be exporting one by one.

Differential Revision: https://reviews.llvm.org/D78972
2020-10-29 14:44:06 -07:00
Jim Ingham a37672e2db Mark the execution of stop-hooks as non-interactive.
The intention is not to allow stop-hook commands to query the
user, so this is correct.  It also works around a deadlock in
switching to the Python Session to execute python based commands
in the stop hook when the Debugger stdin is backed by a FILE *.

Differential Revision: https://reviews.llvm.org/D90332
2020-10-29 14:41:53 -07:00
Christian Sigg db7129a005 [mlir][gpu] Add pass to make GPU ops within a region execute asynchronously.
Do not use the pass yet, except in a test.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D89937
2020-10-29 22:17:50 +01:00
Christian Sigg fce99e5f73 [mlir][gpu] Handle async in gpu.launch_func lowering.
For the synchronous case, destroy the stream after synchronization.

Sneak in a unrelated change to report why the gpu.wait conversion pattern didn't match.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D89933
2020-10-29 22:16:42 +01:00
Nikita Popov 6c2ad4cf87 [SDAG] Extract helper to determine neutral element (NFC)
Make the existing VECREDUCE based code more generic, but expressing
it in terms of the neutral value of the base opcode instead.
2020-10-29 22:05:06 +01:00
Stefanos Baziotis a3345300b6 [LCSSA] Doc for special treatment of PHIs
Differential Revision: https://reviews.llvm.org/D89739
2020-10-29 22:50:07 +02:00
Christian Sigg 3556114083 [mlir][gpu] Allow gpu.launch_func to be async.
This is a roll-forward of rGec7780ebdab4, now that the remaining
gpu.launch_func have been converted to custom form in rGb22f111023ba.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D90420
2020-10-29 21:48:38 +01:00
Nikita Popov 20b386aae0 [LoopUtils] Fix neutral value for vector.reduce.fadd
Use -0.0 instead of 0.0 as the start value. The previous use of 0.0
was fine for all existing uses of this function though, as it is
always generated with fast flags right now, and thus nsz.
2020-10-29 21:45:13 +01:00
Ilya Bukonkin 2c0cbc47ca GetModule, GetExeModule methods added 2020-10-29 23:44:51 +03:00
Florian Hahn 1922570489 [SLP] Consider alternatives for cost of select instructions.
Some architectures do not have general vector select instructions (e.g.
AArch64). But some cmp/select patterns can be vectorized using other
instructions/intrinsics.

One example is using min/max instructions for certain patterns.

This patch updates the cost calculations for selects in the SLP
vectorizer to consider using min/max intrinsics.

This patch does not change SLP vectorizer's codegen itself to actually
generate those intrinsics, but relies on the backends to lower the
vector cmps & selects. This keeps things simple on the SLP side and
works well in practice for AArch64.

This exposes additional SLP vectorization opportunities in some
benchmarks on AArch64 (-O3 -flto).

Metric: SLP.NumVectorInstructions

Program                                        base    slp     diff
 test-suite...ications/JM/ldecod/ldecod.test   502.00  697.00  38.8%
 test-suite...ications/JM/lencod/lencod.test   1023.00 1414.00 38.2%
 test-suite...-typeset/consumer-typeset.test    56.00   65.00  16.1%
 test-suite...6/464.h264ref/464.h264ref.test   804.00  822.00   2.2%
 test-suite...006/453.povray/453.povray.test   3335.00 3357.00  0.7%
 test-suite...CFP2000/177.mesa/177.mesa.test   2110.00 2121.00  0.5%
 test-suite...:: External/Povray/povray.test   2378.00 2382.00  0.2%

Reviewed By: RKSimon, samparker

Differential Revision: https://reviews.llvm.org/D89969
2020-10-29 20:39:50 +00:00
Thomas Lively 6214be3a4a [WebAssembly] Remove unused FileCheck test prefixes
This commit removes unused FileCheck prefixes from WebAssembly test files to
avoid causing test failures once FileCheck disallows unused prefixes by default.
See D90281 and the corresponding llvm-dev thread for context.

Reviewed By: aardappel

Differential Revision: https://reviews.llvm.org/D90416
2020-10-29 13:37:55 -07:00
Nikita Popov a5f172927d [SDAG] Fix neutral value for vecreduce_fadd
The neutral value for FADD is -0.0, not 0.0, so this is what we
need to pad vectors with.
2020-10-29 21:27:59 +01:00
Nikita Popov fa48ff3fc9 [CodeGen] Fix neutral value of vecreduce fadd in tests (NFC)
The neutral value is -0.0, not 0.0. This doesn't matter for "fast"
reductions due to nsz, but does matter for reassoc-only and seq
reductions.

Change tests to mostly use -0.0 where the neutral value was intended,
and add some additional test coverage in some places. Also update
LangRef to use the right value.
2020-10-29 21:26:14 +01:00
Christian Sigg b22f111023 [mlir][gpu] NFC: Change gpu.launch_func ops to custom format.
This should fix the reason for the failures after ec7780ebda. I will roll forward in a separate change.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D90410
2020-10-29 21:21:30 +01:00
Tony 661797bd76 [AMDGPU] Update AMD GPU documentation
- AMDGPUUsage.rst: Correct AMD GPU DWARF address space table address
  sizes which are in bits and not bytes.

- clang/.../Options.td: Improve description of AMD GPU options.

- Re-generate ClangComamndLineReference.rst from clang/.../Options.td .

Differential Revision: https://reviews.llvm.org/D90364
2020-10-29 20:12:47 +00:00
Alex Orlov 8aaafa06b2 Added remotely ran compiler-rt tests.
Use LLVM/utils/remote-exec.py to run compiler-rt tests remotely on the target.

Reviewed By: vvereschaka

Differential Revision: https://reviews.llvm.org/D90054
2020-10-30 00:11:16 +04:00
Marcel Hlopko 9bb9b737c5 Remove HAVE_VCS_VERSION_INC, not needed
This preprocessor define was meant to be used to conditionally include VCSVersion.inc. However, the define was always set, and it was the content of the header that was conditionally generated. Therefore HAVE_VCS_VERSION_INC should be cleaned up.

Reviewed By: gribozavr2, MaskRay

Differential Revision: https://reviews.llvm.org/D84623
2020-10-29 13:09:05 -07:00
Nikita Popov 91bf172088 [SDAG] Extract helper to get vecreduce base opcode (NFC) 2020-10-29 20:22:22 +01:00
Adhemerval Zanella f93c2b64ed [sanitizer] Disable ASLR for release_shadow_space
On aarch64 with kernel 4.12.13 the test sporadically fails with

RSS at start: 1564, after mmap: 103964, after mmap+set label: 308768, \
after fixed map: 206368, after another mmap+set label: 308768, after \
munmap: 206368
release_shadow_space.c.tmp: [...]/release_shadow_space.c:80: int \
main(int, char **): Assertion `after_fixed_mmap <= before + delta' failed.

It seems on some executions the memory is not fully released, even
after munmap.  And it also seems that ASLR is hurting it by adding
some fragmentation, by disabling it I could not reproduce the issue
in multiple runs.
2020-10-29 16:09:03 -03:00
Peyton, Jonathan L 771f0fb92d [OpenMP] Add NULL check in dispatcher debug output
Patch by Nawrin Sultana

Differential Revision: https://reviews.llvm.org/D90403
2020-10-29 14:08:03 -05:00
Dávid Bolvanský 7a2abf5aca [InferAttrs] Add nocapture/writeonly to string/mem libcalls
One step closer to fix PR47644.

Differential Revision: https://reviews.llvm.org/D89645
2020-10-29 20:06:43 +01:00
Paul-Antoine Arras 05f7b68219 [llvm-libtool-darwin] Add support for LLVM bitcode files
This diff adds support for LLVM bitcode objects to llvm-libtool-darwin.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D88722
2020-10-29 12:00:44 -07:00
Utkarsh Saxena 7df80a1204 [clangd] Add support for multiple DecisionForest model experiments.
With every incremental change, one needs to check-in new model upstream.
This also significantly increases the size of the git repo with every
new model.
Testing and comparing the old and previous model is also not possible as
we run only a single model at any point.

One solution is to have a "staging" decision forest which can be
injected into clangd without pushing it to upstream. Compare the
performance of the staging model with the live model. After a couple of
enhancements have been done to staging model, we can then replace the
live model upstream with the staging model. This reduces upstream churn
and also allows us to compare models with current baseline model.

This is done by having a callback in CodeCompleteOptions which is called
only when we want to use a decision forest ranking model. This allows us
to inject different completion model internally.

Differential Revision: https://reviews.llvm.org/D90014
2020-10-29 19:49:40 +01:00
Craig Topper 22c3837634 [RISCV] Remove include of RISCVRegisterInfo.h from RISCVBaseInfo.h
RISCVRegisterInfo.h is part of the CodeGen layer. The Utils library
is intended to be shared with the MC layer so shouldn't use files
from the CodeGen layer.

The register enum names are already available from
RISCVMCTargetDesc.h. It appears what was coming from this include
was a transitive include of the Register class which I've replaced
with MCRegister. Register has a constructor from MCRegister so it
should be convertible.
2020-10-29 11:39:19 -07:00
Teresa Johnson d124ac0c22 [MemProf] Temporarily disable test failing on a couple bots
I finally see why this test is failing (on now 2 bots). Somehow the path
name is getting messed up, and the "linux" converted to "1". I suspect
there is something in the environment causing the macro expansion in the
test to get messed up:

http://lab.llvm.org:8011/#/builders/112/builds/555/steps/5/logs/FAIL__MemProfiler-x86_64-linux__log_path_test_cpp
http://lab.llvm.org:8011/#/builders/37/builds/275/steps/31/logs/stdio

On the avr bot:
-DPROFILE_NAME_VAR="/home/buildbot/llvm-avr-linux/llvm-avr-linux/stage1/projects/compiler-rt/test/memprof/X86_64LinuxConfig/TestCases/Output/log_path_test.cpp.tmp.log2"

after macros expansions becomes:
/home/buildbot/llvm-avr-1/llvm-avr-1/stage1/projects/compiler-rt/test/memprof/X86_64LinuxConfig/TestCases/Output/log_path_test.cpp.tmp.log2

Similar (s/linux/1/) on the other bot.

Disable it while I investigate
2020-10-29 11:26:21 -07:00
Sylvestre Ledru 5d1eae7d23 Add support of the next Ubuntu (Ubuntu 21.04 - Hirsute Hippo) 2020-10-29 19:11:32 +01:00
Thomas Lively be6f50798e [WebAssembly] Implement SIMD signselect instructions
As proposed in https://github.com/WebAssembly/simd/pull/124, using the opcodes
adopted by V8 in
https://chromium-review.googlesource.com/c/v8/v8/+/2486235/2/src/wasm/wasm-opcodes.h.
Uses new builtin functions and a new target intrinsic exclusively to ensure that
the new instructions are only emitted when a user explicitly opts in to using
them since they are still in the prototyping and evaluation phase.

Differential Revision: https://reviews.llvm.org/D90357
2020-10-29 11:06:20 -07:00
Louis Dionne bffdc241a6 [libc++] Minor cleanup in the test suite 2020-10-29 13:58:02 -04:00
Jody Sankey 5a3077f3a7 [sanitizer][fuchsia] Avoid deprecated syscall.
The zx_clock_get syscall on Fuchsia is deprecated - ref
https://fuchsia.dev/fuchsia-src/reference/syscalls/clock_get
This changes to the recommended replacement; calling zx_clock_read on
the userspace UTC clock.

Reviewed By: mcgrathr, phosek

Differential Revision: https://reviews.llvm.org/D90169
2020-10-29 10:51:59 -07:00