Commit Graph

112968 Commits

Author SHA1 Message Date
Bjorn Pettersson 304877e5ec Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"
Summary:
This reverts SVN r331441 (reapplies r331337), together with a fix
in to handle an already existing fragment expression in the
dbg.value that must be fragmented due to a split PHI node.

This should solve the problem seen in PR37321, which was the
reason for the revert of r331337.

The situation in PR37321 is that we have a PHI node like this

   %u.sroa = phi i80 [ %u.sroa.x, %if.x ],
                     [ %u.sroa.y, %if.y ],
                     [ %u.sroa.z, %if.z ]

and a dbg.value like this

  call void @llvm.dbg.value(metadata i80 %u.sroa,
                            metadata !13,
                            metadata !DIExpression(DW_OP_LLVM_fragment, 0, 80))

The phi node is split into three 32-bit PHI nodes

  %30:gr32 = PHI %11:gr32, %bb.4, %14:gr32, %bb.5, %27:gr32, %bb.8
  %31:gr32 = PHI %12:gr32, %bb.4, %15:gr32, %bb.5, %28:gr32, %bb.8
  %32:gr32 = PHI %13:gr32, %bb.4, %16:gr32, %bb.5, %29:gr32, %bb.8

but since the original value only is 80 bits we need to adjust the size
of the last fragment expression, and with this patch we get

  DBG_VALUE debug-use %30:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 0, 32)
  DBG_VALUE debug-use %31:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 32, 32)
  DBG_VALUE debug-use %32:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 64, 16)

Reviewers: vsk, aprantl, mstorsjo

Reviewed By: aprantl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46384

llvm-svn: 331464
2018-05-03 17:04:16 +00:00
Simon Pilgrim f7dd6069a5 [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes
llvm-svn: 331453
2018-05-03 13:27:10 +00:00
Tim Northover 28e0a6f7dd ARM: don't try to over-align large vectors as arguments.
By default LLVM thinks very large vectors get aligned to their size when
passed across functions. Unfortunately no-one told the ARM backend so it
doesn't trigger stack realignment and so accesses can cause the usual
misalignment issues (e.g. a data abort).

This changes the ABI alignment to the stack alignment, which in practice
(and as a bonus) also coincides with the alignment "natural" vectors get.

llvm-svn: 331451
2018-05-03 12:54:25 +00:00
Piotr Padlewski c77ab8ef2f perform DSE through launder.invariant.group
Summary:
Alias Analysis knows that llvm.launder.invariant.group
returns pointer that mustalias argument, but this information
wasn't used, therefor we didn't DSE through launder.invariant.group

Reviewers: chandlerc, dberlin, bogner, hfinkel, efriedma

Reviewed By: dberlin

Subscribers: amharc, llvm-commits, nlewycky, rsmith

Differential Revision: https://reviews.llvm.org/D31581

llvm-svn: 331449
2018-05-03 11:03:53 +00:00
Piotr Padlewski 5dde809404 Rename invariant.group.barrier to launder.invariant.group
Summary:
This is one of the initial commit of "RFC: Devirtualization v2" proposal:
https://docs.google.com/document/d/16GVtCpzK8sIHNc2qZz6RN8amICNBtvjWUod2SujZVEo/edit?usp=sharing

Reviewers: rsmith, amharc, kuhar, sanjoy

Subscribers: arsenm, nhaehnle, javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D45111

llvm-svn: 331448
2018-05-03 11:03:01 +00:00
Simon Pilgrim 39196a1dd3 [X86][AVX512] VPAVG instructions should be tagged as SchedWriteVecALU
llvm-svn: 331446
2018-05-03 10:53:17 +00:00
Simon Pilgrim 93c878c76b [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM scheduler classes
Also retagged VDBPSADBW instructions as SchedWritePSADBW instead of SchedWriteVecIMul which matches the behaviour on SkylakeServer (the only thing that supports it...)

llvm-svn: 331445
2018-05-03 10:31:20 +00:00
Simon Pilgrim 342ac8cd7e [X86] Update MMX instructions to be tagged with X86SchedWriteWidths types
llvm-svn: 331443
2018-05-03 09:11:32 +00:00
Martin Storsjo 67fdea490d Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"
This reverts SVN r331337, see PR37321 for details on the regression
it introduced.

llvm-svn: 331441
2018-05-03 07:09:33 +00:00
Clement Courbet 6794660828 [TableGen][NFC] Make ResourceCycles definitions more explicit.
https://reviews.llvm.org/D46356

llvm-svn: 331439
2018-05-03 06:08:47 +00:00
Craig Topper 856fd68690 [LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the left hand side of the 'and' matches the left hand side of the 'subtract'
llvm-svn: 331437
2018-05-03 05:48:49 +00:00
Craig Topper 8ef2abdbc4 [LoopIdiomRecognize] Remove unnecessary cast from BinaryOperator to Instruction. NFC
BinaryOperator is a sub class of Instruction. We don't need an explicit cast back to Instruction.

llvm-svn: 331432
2018-05-03 05:00:18 +00:00
Max Kazantsev 58fce7e54b Re-enable "[SCEV] Make computeExitLimit more simple and more powerful"
This patch was temporarily reverted because it has exposed bug 37229 on
PowerPC platform. The bug is unrelated to the patch and was just a general
bug in the optimization done for PowerPC platform only. The bug was fixed
by the patch rL331410.

This patch returns the disabled commit since the bug was fixed.

llvm-svn: 331427
2018-05-03 02:37:55 +00:00
Petr Hosek 87f1343a73 [Support] Support building LLVM for Fuchsia
These are necessary changes to support building LLVM for Fuchsia.
While these are not sufficient to run on Fuchsia, they are still
useful when cross-compiling LLVM libraries and runtimes for Fuchsia.

Differential Revision: https://reviews.llvm.org/D46345

llvm-svn: 331423
2018-05-03 01:38:49 +00:00
Shoaib Meenai a07295f977 [ObjCARC] Convert an if to an early continue. NFC
This reduces nesting and makes the logic slightly easier to follow.

Differential Revision: https://reviews.llvm.org/D46371

llvm-svn: 331422
2018-05-03 01:20:36 +00:00
Nemanja Ivanovic 61ffbf21cd Commit r331416 breaks the big-endian PPC bot. On the big endian build, we
actually encounter constants wider than 64-bits. Add the guard to prevent
tripping the assert.

llvm-svn: 331420
2018-05-03 01:04:13 +00:00
Chandler Carruth e74c354d12 [gcov] Switch to an explicit if clunky array to satisfy some compilers
on various build bots that are unhappy with using makeArrayRef with an
initializer list.

llvm-svn: 331418
2018-05-03 00:11:03 +00:00
Michael Berg 7d1b25d053 MachineInst support mapping SDNode fast math flags for support in Back End code generation
Summary:
Machine Instruction flags for fast math support and MIR print support


Reviewers: spatel, arsenm

Reviewed By: arsenm

Subscribers: wdng

Differential Revision: https://reviews.llvm.org/D45781

llvm-svn: 331417
2018-05-03 00:07:56 +00:00
Nemanja Ivanovic 01e2e79abf [PowerPC] Implement isMaskAndCmp0FoldingBeneficial
Sinking the and closer to a compare against zero is beneficial on PPC as it
allows us to emit record-form instructions. In the future, we may expand this
to a larger set of operations that feed compares against zero since PPC has
lots of record-form instructions.

Differential revision: https://reviews.llvm.org/D46060

llvm-svn: 331416
2018-05-02 23:55:23 +00:00
Sam Clegg 4d57fbd02a [WebAssembly] MC: Create and use first class section symbols
Differential Revision: https://reviews.llvm.org/D46335

llvm-svn: 331413
2018-05-02 23:11:38 +00:00
Sam Clegg 87cc4dbde7 [MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer.
This code previously existed only in MCMachOStreamer but is
useful for WebAssembly too.  See: D46335

Differential Revision: https://reviews.llvm.org/D46297

llvm-svn: 331412
2018-05-02 23:01:10 +00:00
Nemanja Ivanovic 2139e99e47 [PowerPC] No CTR loop if the candidate exiting block is in a different loop
The CTR loops pass will insert the decrementing branch instruction in an exiting
block for the loop being transformed. However if that block is part of another
loop as well (whether a nested loop or with irreducible CFG), it is not valid
to use that exiting block. In fact, if the loop hass irreducible CFG, we don't
bother analyzing it and we just bail on the transformation. In practice, this
doesn't lead to a noticeable reduction in the number of loops transformed by
this pass.

Fixes https://bugs.llvm.org/show_bug.cgi?id=37229

Differential Revision: https://reviews.llvm.org/D46162

llvm-svn: 331410
2018-05-02 22:56:04 +00:00
Chandler Carruth 71c3a3fac5 [GCOV] Emit the writeout function as nested loops of global data.
Summary:
Prior to this change, LLVM would in some cases emit *massive* writeout
functions with many 10s of 1000s of function calls in straight-line
code. This is a very wasteful way to represent what are fundamentally
loops and creates a number of scalability issues. Among other things,
register allocating these calls is extremely expensive. While D46127 makes this
less severe, we'll still run into scaling issues with this eventually. If not
in the compile time, just from the code size.

Now the pass builds up global data structures modeling the inputs to
these functions, and simply loops over the data structures calling the
relevant functions with those values. This ensures that the code size is
a fixed and only data size grows with larger amounts of coverage data.

A trivial change to IRBuilder is included to make it easier to build
the constants that make up the global data.

Reviewers: wmi, echristo

Subscribers: sanjoy, mcrosier, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D46357

llvm-svn: 331407
2018-05-02 22:24:39 +00:00
Simon Pilgrim 350c22c587 [X86][SNB] Fix scheduling of MMX integer multiply instructions.
The entries were being bound to the wrong class.

llvm-svn: 331388
2018-05-02 19:26:14 +00:00
Simon Pilgrim 6732f6ea51 [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM and YMM/ZMM scheduler classes
llvm-svn: 331386
2018-05-02 18:48:23 +00:00
Martin Storsjo d0b5034b8a [COFF, ARM64] Hook up a few remaining relocations
Differential Revision: https://reviews.llvm.org/D46355

llvm-svn: 331384
2018-05-02 18:24:37 +00:00
Farhana Aleen 07e612340f [AMDGPU] A trivial fix for a buildbot failure caused by "commit 224a839fcbbead221f872cd32a1dd0c308d37299".
Author: FarhanaAleen
llvm-svn: 331383
2018-05-02 18:16:39 +00:00
Daniel Sanders 8d0d1aa229 [reassociate] Fix excessive revisits when processing long chains of reassociatable instructions.
Summary:
Some of our internal testing detected a major compile time regression which I've
tracked down to:
    r278938 - Revert "Reassociate: Reprocess RedoInsts after each inst".
It appears that processing long chains of reassociatable instructions causes
non-linear (potentially exponential) growth in the number of times an
instruction is revisited. For example, the included test revisits instructions
220 times in a 20-instruction test.

It appears that r278938 reversed the order instructions were visited and that
this is preventing scheduled revisits from being cancelled as a result of
visiting the instructions naturally during normal processing. However, simply
reversing the order also harmed the generated code. Upon closer inspection, it
was discovered that revisits occurred in the opposite order to the first pass
(Thanks to escha for spotting that).

This patch makes the revisit order consistent with the first pass which allows
more revisits to be cancelled. This does appear to have a small impact on the
generated code in few cases but it significantly reduces compile-time.

After this patch, our internal test that was most affected by the regression
dropped from ~2 million revisits to ~4k resulting in Reassociate having 0.46%
of the runtime it had before (99.54% improvement).

Here's the summaries reported by lnt for the LLVM test-suite with --benchmarking-only:
| metric         | geomean before patch | geomean after patch | delta   |
| -----          | -----                | -----               | -----   |
| compile time   | 0.1956               | 0.1261              | -35.54% |
| execution time | 0.3240               | 0.3237              | -       |
| code size      | 7365.4459            | 7365.6079           | -       |

The results have a few wins and losses on compile-time, mostly in the +/- 2.5% range. There was one outlier though:
| Performance Regressions - compile_time | Δ | Previous | Current |
| MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 9.82% | 2.0473 | 2.2483 |

Reviewers: javed.absar, dberlin

Reviewed By: dberlin

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45734

llvm-svn: 331381
2018-05-02 17:59:16 +00:00
Simon Pilgrim 819f218f07 [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes with more common default values
llvm-svn: 331380
2018-05-02 17:58:50 +00:00
Krzysztof Parzyszek 5e3aba8251 Add assertion to padding size calculation, NFC
The size of an object cannot be less than the emitted size of all the
contained elements. This would cause an overflow in padding size
calculation. Add an assert to catch this.

Patch by Suyog Sarda.

llvm-svn: 331376
2018-05-02 17:20:22 +00:00
Farhana Aleen 150cb6d91a Revert "[AMDGPU] performAddCombine should run after DAG is legalized."
This reverts commit 6b97d2995566b4dddd6bf0d75579ff44501d4494.

llvm-svn: 331371
2018-05-02 16:48:52 +00:00
Simon Pilgrim a3a4df3708 [X86] Convert most remaining XOP uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
llvm-svn: 331369
2018-05-02 16:25:41 +00:00
Farhana Aleen 2f4100f56e [AMDGPU] performAddCombine should run after DAG is legalized.
Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization
         in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with
         illegal types.

Author: FarhanaAleen

Reviewed By: rampitec

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D46337

llvm-svn: 331368
2018-05-02 16:24:10 +00:00
Simon Pilgrim a53d330890 Fix line-endings. NFCI.
llvm-svn: 331367
2018-05-02 16:16:24 +00:00
Clement Courbet d2ff5fb536 Re-land rL331357 "[X86] Fix scheduling info for VMPSADBWYrmi."
Without the rebase mess.

https://reviews.llvm.org/D46356

llvm-svn: 331362
2018-05-02 14:35:48 +00:00
Simon Pilgrim 86d9f23ded [X86] Cleanup WriteFMul scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.

llvm-svn: 331360
2018-05-02 14:25:32 +00:00
Simon Pilgrim f53ee8e640 Fix '32-bit shift implicitly converted to 64 bits' warning by using APInt::setBit instead.
llvm-svn: 331359
2018-05-02 14:22:30 +00:00
Clement Courbet 0f1da8f365 Revert rL331355 "[X86] Fix scheduling info for VMPSADBWYrmi."
It contains unrelated changes.

llvm-svn: 331357
2018-05-02 13:54:38 +00:00
Clement Courbet a1a3095d88 [X86] Fix scheduling info for (V?)SQRTPDm on silvermont.
https://reviews.llvm.org/D46356

llvm-svn: 331356
2018-05-02 13:46:14 +00:00
Clement Courbet eeb2123a83 [X86] Fix scheduling info for VMPSADBWYrmi.
https://reviews.llvm.org/D46356

llvm-svn: 331355
2018-05-02 13:40:48 +00:00
Clement Courbet da54914cde [MIPS] Fix DIV/DIVU scheduling classes.
https://reviews.llvm.org/D46356.

llvm-svn: 331354
2018-05-02 13:37:28 +00:00
Simon Pilgrim a1f1a3bf94 [X86] Convert most remaining AVX512 uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
We've dealt with the majority already.

llvm-svn: 331353
2018-05-02 13:32:56 +00:00
Sander de Smalen 659a48cd38 [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D46270

llvm-svn: 331352
2018-05-02 13:32:39 +00:00
Simon Tatham 6a02604ee4 [TableGen] Don't quote variable name when printing !foreach.
An input !foreach expression such as !foreach(a, lst, !add(a, 1))
would be re-emitted by llvm-tblgen -print-records with the first
argument in quotes, giving !foreach("a", lst, !add(a, 1)), which isn't
valid TableGen input syntax.

Reviewers: nhaehnle

Reviewed By: nhaehnle

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46352

llvm-svn: 331351
2018-05-02 13:17:26 +00:00
Sander de Smalen 57da042e32 [AArch64][SVE] Asm: Support for scatter ST1 store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46248

llvm-svn: 331349
2018-05-02 13:00:30 +00:00
Simon Dardis 694fde215e Revert "[mips] Correct the predicates of sign extension instructions"
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.

This reverts r331346.

llvm-svn: 331348
2018-05-02 12:35:29 +00:00
Simon Pilgrim e8671ef434 [X86] Convert most remaining uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
We've dealt with the majority already.

llvm-svn: 331347
2018-05-02 12:27:54 +00:00
Simon Dardis 7a36495bf7 [mips] Correct the predicates of sign extension instructions
And eliminate the duplication of those instructions for microMIPS32r6.

llvm-svn: 331346
2018-05-02 12:25:33 +00:00
Sander de Smalen 414d2358a4 [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D46269

llvm-svn: 331343
2018-05-02 11:48:49 +00:00
Florian Hahn 5912c667b0 [LoopInterchange] Update some loops to use range base for loops (NFC).
llvm-svn: 331342
2018-05-02 10:53:04 +00:00