Commit Graph

427434 Commits

Author SHA1 Message Date
Nikolas Klauser 2fcf99d703 [libc++] Implement P0174R2 (Deprecating Vestigial Library Parts in C++17)
Reviewed By: ldionne, Mordante, #libc

Spies: jwakely, libcxx-commits

Differential Revision: https://reviews.llvm.org/D127387
2022-06-21 08:22:44 +02:00
Kazu Hirata 6d5fc1e3d5 [mlir] Don't use Optional::getValue (NFC) 2022-06-20 23:20:25 -07:00
Markus Lavin 3815ae29b5 [machinesink] fix debug invariance issue
Do not include debug instructions when comparing block sizes with
thresholds.

Differential Revision: https://reviews.llvm.org/D127208
2022-06-21 08:13:09 +02:00
Kazu Hirata ca4af13e48 [clang] Don't use Optional::getValue (NFC) 2022-06-20 22:59:26 -07:00
Kazu Hirata 7a47ee51a1 [llvm] Don't use Optional::getValue (NFC) 2022-06-20 22:45:45 -07:00
Chen Zheng 9cfbe7bbfe [PowerPC][ctrloop] handles calls in preheader before MTCTRloop 2022-06-21 01:22:39 -04:00
Argyrios Kyrtzidis bb095880f8 [Support/BLAKE3] Do a CMake check for the `-mavx512vl` flag before applying it 2022-06-20 22:04:14 -07:00
Shraiysh Vaishay 23fec3405b [mlir][OpenMP] Add omp.taskgroup operation
This patch adds omp.taskgroup operation according to OpenMP 5.0 2.17.6.

Also added tests for the same.

Reviewed By: kiranchandramohan, peixin

Differential Revision: https://reviews.llvm.org/D127250
2022-06-21 10:17:24 +05:30
Shraiysh Vaishay c858f4dbd5 [flang][OpenMP] Fix firstprivate with barrier
This patch fixes the unintentional data race in firstprivate
implementation. There is a Read-Write race when one thread tries
to copy the value inside the omp.parallel region while other
thread modifies it from inside the region (using pointers or
some other form of indirect access).

For detailed discussion please refer to [[ https://discourse.llvm.org/t/issues-with-the-current-implementation-of-privatization-in-openmp-with-fortran/62335 | discourse ]].

Reviewed By: kiranchandramohan, peixin, NimishMishra

Differential Revision: https://reviews.llvm.org/D125689
2022-06-21 10:06:05 +05:30
Argyrios Kyrtzidis 34362f96d2 [Support/BLAKE3] Enable the SIMD implementations for macOS universal builds
To accomodate macOS universal configuration include the assembly files
and `blake3_neon.c` without a CMake check but instead guard their source
with architecture "#ifdef" checks.

Differential Revision: https://reviews.llvm.org/D128132
2022-06-20 21:18:44 -07:00
Craig Topper e01353f816 [RISCV] Add RISCVISD opcode for PseudoAddTPRel.
Use it along with RISCVISD::HI and ADD_LO to avoid emitting
MachineSDNodes during lowering.
2022-06-20 20:56:52 -07:00
Craig Topper 59cde2133d Recommit "[RISCV] Enable subregister liveness tracking for RVV."
The failure that caused the previous revert has been fixed
by https://reviews.llvm.org/D126048

Original commit message:

RVV makes heavy use of subregisters due to LMUL>1 and segment
load/store tuples. Enabling subregister liveness tracking improves the quality
of the register allocation.

I've added a command line that can be used to turn it off if it causes compile
time or functional issues. I used the command line to keep the old behavior
for one interesting test case that was testing register allocation.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D128016
2022-06-20 20:46:06 -07:00
Serguei Katkov 163c77b2e0 [AARCH64 folding] Do not fold any copy with NZCV
There is no instruction to fold NZCV, so, just do not do it.

Without the fix the added test case crashes with an assert
"Mismatched register size in non subreg COPY"

Reviewed By: danilaml
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D127294
2022-06-21 10:38:49 +07:00
Kazu Hirata d66cbc565a Don't use Optional::hasValue (NFC) 2022-06-20 20:26:05 -07:00
Kazu Hirata 0916d96d12 Don't use Optional::hasValue (NFC) 2022-06-20 20:17:57 -07:00
Kazu Hirata 064a08cd95 Don't use Optional::hasValue (NFC) 2022-06-20 20:05:16 -07:00
LLVM GN Syncbot b89f483064 [gn build] Port a71fe49bb5 2022-06-21 02:57:40 +00:00
Chen Zheng a71fe49bb5 [PowerPC] add a new pass to expand ctr loop pseudos
This patch implements a new way to generate the CTR loops. Now the
intrinsics inserted in hardware loop pass will be mapped to pseudo
instructions and these pseudo instructions will be expanded to CTR
loop or normal compare+branch loop in this post ISEL pass.

Reviewed By: lkail

Differential Revision: https://reviews.llvm.org/D122125
2022-06-20 22:57:24 -04:00
Craig Topper 16d3a82de5 [RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes.
Use it in place of VSELECT_VL+VRGATHER*_VL.

This simplifies the isel patterns.

Overall, I think trying to match select+op to create masked instructions
in isel doesn't scale. We either need to do it in DAG combine, pre-isel
peepole, or post-isel peephole. I don't yet know which is the right
answer, but for this case it seemed best to be able to request the
masked form directly from lowering.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D128023
2022-06-20 18:58:24 -07:00
chenglin.bi 6c951c5ee6 [SelectionDAG][DAGCombiner] Reuse exist node by reassociate
When already have (op N0, N2), reassociate (op (op N0, N1), N2) to (op (op N0, N2), N1) to reuse the exist (op N0, N2)

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D122539
2022-06-21 09:45:19 +08:00
Luo, Yuanke 44e8a205f4 [fastregalloc] Enhance the heuristics for liveout in self loop.
For below case, virtual register is defined twice in the self loop. We
don't need to spill %0 after the third instruction `%0 = def (tied %0)`,
because it is defined in the second instruction `%0 = def`.

1 bb.1
2 %0 = def
3 %0 = def (tied %0)
4 ...
5 jmp bb.1

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D125079
2022-06-21 09:18:49 +08:00
Mogball d883a02a7c [mlir][ods] Remove StructAttr
Depends on D127373

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D127375
2022-06-21 01:10:05 +00:00
Phoebe Wang edcc68e86f [X86] Make sure SF is updated when optimizing for `jg/jge/jl/jle`
This fixes issue #56103.

Reviewed By: mingmingl

Differential Revision: https://reviews.llvm.org/D128122
2022-06-21 09:09:27 +08:00
Brad Smith 7c5957aedb [Driver] Pass -X to ld for riscv64-fuchsia
D127826, add support for Fuchsia which uses lld on riscv64

Reviewed By: MaskRay, phosek

Differential Revision: https://reviews.llvm.org/D128134
2022-06-20 21:05:01 -04:00
Jeffrey Tan 5109de2da2 Fix build break introduced by https://reviews.llvm.org/D127702
Fix build break introduced by https://reviews.llvm.org/D127702

Differential Revision: https://reviews.llvm.org/D128234
2022-06-20 17:31:26 -07:00
archsaxe 523adafbd2 [test][AlwaysInline]:Correct comment and file check for always-inline.ll
This fixes a useless filecheck and wrong comment for always-inline.ll. Testing
has been done using ninja check-llvm and llvm-lit always-inline.ll --show-all.

Reviewed By: modimo, hoy

Differential Revision: https://reviews.llvm.org/D127815
2022-06-20 16:53:31 -07:00
Pengxuan Zheng dec1614791 [LLD][COFF] Ignore /pdbcompress flag
Microsoft does not seem to document the flag. Ignoring it for now is probably
better than getting an unknown flag error.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D128231
2022-06-20 16:48:39 -07:00
lewuathe 0bae40eff6 [mlir][math] Lower cos,sin to libm
Lower math.cos and math.sin to libm

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D128028
2022-06-21 08:38:07 +09:00
Jeffrey Tan 8c6e138aa8 Support logpoints in lldb-vscode
This patch implements VSCode DAP logpoints feature (also called tracepoint
in other VS debugger).
This will provide a convenient way for user to do printf style logging
debugging without pausing debuggee.

Differential Revision: https://reviews.llvm.org/D127702
2022-06-20 16:22:12 -07:00
Nico Weber 0cc7ad4175 Revert "[lld-macho] Show source information for undefined references"
This reverts commit cd7624f153.
See https://reviews.llvm.org/D128184#3597534
2022-06-20 19:15:57 -04:00
Daniel Bertalan cd7624f153 [lld-macho] Show source information for undefined references
The error used to look like this:

  ld64.lld: error: undefined symbol: _foo
  >>> referenced by /path/to/bar.o:(symbol _baz+0x4)

If DWARF line information is available, we now show where in the source
the references are coming from:

  ld64.lld: error: unreferenced symbol: _foo
  >>> referenced by: bar.cpp:42 (/path/to/bar.cpp:42)
  >>>                /path/to/bar.o:(symbol _baz+0x4)

Differential Revision: https://reviews.llvm.org/D128184
2022-06-20 18:49:42 -04:00
Kazushi (Jam) Marukawa 5ba0a9571b [Clang][VE] Add missing intrinsics
Add missing intrinsics and tests for them.  An expanding  macro
from _vel_pack_f32p to __builtin_ve_vl_pack_f32p and others is
already defined in clang/lib/Headers/velintrin.h.

Reviewed By: efocht

Differential Revision: https://reviews.llvm.org/D128120
2022-06-21 07:30:36 +09:00
Maksim Panchenko 30a6d3ada6 [BOLT][TEST] Fix stack alignment in section-reloc-with-addend.s
Misaligned stack can cause a runtime crash.

Reviewed By: Amir

Differential Revision: https://reviews.llvm.org/D128227
2022-06-20 14:47:37 -07:00
Martin Storsjö c9fc4336d4 [lldb] Fix building with GCC 7 2022-06-21 00:19:09 +03:00
Ruiling Song 732eed40fd [AMDGPU] Mark GFX11 dual source blend export as strict-wqm
The instructions that generate the source of dual source blend export
should run in strict-wqm. That is if any lane in a quad is active,
we need to enable all four lanes of that quad to make the shuffling
operation before exporting to dual source blend target work correctly.

Differential Revision: https://reviews.llvm.org/D127981
2022-06-20 21:58:12 +01:00
Piotr Sobczak 29621c13ef [AMDGPU] Tag GFX11 LDS loads as using strict_wqm
LDS_PARAM_LOAD and LDS_DIRECT_LOAD use EXEC per quad
(if any pixel is enabled in the quad, data is written
to all 4 pixels/threads in the quad).

Tag LDS_PARAM_LOAD and LDS_DIRECT_LOAD as using strict_wqm
to enforce this and avoid lane clobbering issues.
Note that only the instruction itself is tagged.
The implicit uses of these do not need to be set WQM.
The reduces unnecessary WQM calculation of M0.

Differential Revision: https://reviews.llvm.org/D127977
2022-06-20 21:58:12 +01:00
Jay Foad 13107c2770 [AMDGPU] Add support for GFX11 LDSDIR hazards
Detect LDS direct WAR/WAW hazards and compute values for
wait_vdst (va_vdst) parameter.  Where appropriate this
raises wait_vdst from the default 0 to allow concurrent
issue of LDS direct with VALU execution.

Also detect LDS direct versus VMEM source VGPR hazards
and insert vm_vsrc=0 waits using s_waitcnt_depctr.

Differential Revision: https://reviews.llvm.org/D127963
2022-06-20 21:58:12 +01:00
Philip Reames bbf3fd4af1 [BasicTTI] Return Invalid for scalable vectors reaching getScalarizationOverhead
If we would scalarize a fixed vector, we know we can't do so for a scalable one.  However, there's no need to crash, we can instead simply return a invalid cost which will work its way through the computation (since invalid is sticky), and the client should bail out.

Sorry for the lack of test here.  The particular codepath I saw this reached on was the result of another bug.
2022-06-20 13:19:11 -07:00
Amir Ayupov 31e2bba155 [TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE
Make Offsets and OpcodeOperandTypes tables human-readable by printing the
instruction name before the operand list.

In effect, this makes debugging generated `getOperandType` possible.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D127931
2022-06-20 13:15:52 -07:00
Philip Reames 0aebd1d875 [RISCV] Fix crash when costing scalable gather/scatter of pointer
This was a bug introduced in d764aa. A pointer type is not a primitive type, and thus we were ending up dividing by zero when computing VLMax.

Differential Revision: https://reviews.llvm.org/D128219
2022-06-20 12:50:42 -07:00
Mehdi Chinoune df6291a666 [CMake][MSVC] Compile with `/permissive-`
This turns off a bunch of non-standard behaviors in MSVC. LLVM, as a
portable codebase, should build correctly without those behaviors. Note
that `/permissive-` implies `/Zc:strictStrings` and `/Zc:rvalueCast`.

See also:
https://docs.microsoft.com/en-us/cpp/build/reference/permissive-standards-conformance

Differential Revision: https://reviews.llvm.org/D125263
2022-06-20 12:42:51 -07:00
Amir Ayupov 0198448a4b Revert "[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE"
This reverts commit 4cd416193c.
2022-06-20 12:42:08 -07:00
Florian Hahn 6dd772d348
[ConstraintElimination] Move logic to get a constraint to helper (NFC). 2022-06-20 21:34:07 +02:00
Nemanja Ivanovic e09f6ff3c1 [PowerPC] Disable automatic generation of STXVP
There are instances where using paired vector stores leads to significant
performance degradation due to issues with store forwarding.To avoid falling
into this trap with compiler - generated code, we will not emit these
instructions unless the user requests them explicitly(with a builtin or by
specifying the option).

Reviewed By : lei, amyk, saghir

Differential Revision: https://reviews.llvm.org/D127218
2022-06-20 14:30:29 -05:00
Amir Ayupov 4cd416193c [TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE
Make Offsets and OpcodeOperandTypes tables human-readable by printing the
instruction name before the operand list.

In effect, this makes debugging generated `getOperandType` possible.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D127931
2022-06-20 12:24:01 -07:00
Jakob Johnson 50f9367960 Add LoadTraceFromFile to SBDebugger and SBTrace
Add trace load functionality to SBDebugger via the `LoadTraceFromFile` method.
Update intelpt test case class to have `testTraceLoad` method so we can take advantage of
the testApiAndSB decorator to test both the CLI and SB without duplicating code.

Differential Revision: https://reviews.llvm.org/D128107
2022-06-20 11:54:47 -07:00
Kazu Hirata ad7ce1e769 Don't use Optional::hasValue (NFC) 2022-06-20 11:49:10 -07:00
Kazu Hirata 5413bf1bac Don't use Optional::hasValue (NFC) 2022-06-20 11:33:56 -07:00
Kazu Hirata 037f09959a [mlir] Don't use Optional::hasValue (NFC) 2022-06-20 11:22:37 -07:00
David Green c0ecbfa4fd [AArch64] Known bits for AArch64ISD::DUP
An AArch64ISD::DUP is just a splat, where the known bits for each lane
are the same as the input. This teaches that to computeKnownBitsForTargetNode.

Problems arise for constants though, as a constant BUILD_VECTOR can be
lowered to an AArch64ISD::DUP, which SimplifyDemandedBits would then
turn back into a constant BUILD_VECTOR leading to an infinite cycle.
This has been prevented by adding a isTargetCanonicalConstantNode node
to prevent the conversion back into a BUILD_VECTOR.

Differential Revision: https://reviews.llvm.org/D128144
2022-06-20 19:11:57 +01:00