Craig Topper
|
fe9179fa4f
|
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
llvm-svn: 141505
|
2011-10-09 07:31:39 +00:00 |
|
Craig Topper
|
d9cfddc5cd
|
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
llvm-svn: 141358
|
2011-10-07 07:02:24 +00:00 |
|
Craig Topper
|
bf136764ae
|
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
llvm-svn: 141354
|
2011-10-07 05:53:50 +00:00 |
|
Craig Topper
|
f18c896337
|
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
llvm-svn: 141065
|
2011-10-04 06:30:42 +00:00 |
|
Craig Topper
|
786bdb9e14
|
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
llvm-svn: 141007
|
2011-10-03 17:28:23 +00:00 |
|
Craig Topper
|
0d0be47d03
|
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
llvm-svn: 140997
|
2011-10-03 08:14:29 +00:00 |
|
Craig Topper
|
285bc34089
|
Test updates that were supposed to go with r140993.
llvm-svn: 140994
|
2011-10-03 07:53:59 +00:00 |
|
Craig Topper
|
7aea69d949
|
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
llvm-svn: 140974
|
2011-10-02 21:08:12 +00:00 |
|
Craig Topper
|
21c33657d6
|
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
llvm-svn: 140971
|
2011-10-02 16:56:09 +00:00 |
|
Craig Topper
|
d07a59f288
|
Fix disassembling of INVEPT and INVVPID to take operands
llvm-svn: 140955
|
2011-10-01 21:20:14 +00:00 |
|
Craig Topper
|
88cb33e0d4
|
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
llvm-svn: 140954
|
2011-10-01 19:54:56 +00:00 |
|
Craig Topper
|
45faba98b4
|
Fix VEX decoding in i386 mode. Fixes PR11008.
llvm-svn: 140515
|
2011-09-26 05:12:43 +00:00 |
|
Craig Topper
|
526adabe87
|
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
llvm-svn: 140370
|
2011-09-23 06:57:25 +00:00 |
|
Craig Topper
|
6d1872b77a
|
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
llvm-svn: 140299
|
2011-09-22 07:01:50 +00:00 |
|
Craig Topper
|
ee8157cb41
|
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
llvm-svn: 139691
|
2011-09-14 06:41:26 +00:00 |
|
Craig Topper
|
96e00e5a24
|
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
llvm-svn: 139690
|
2011-09-14 05:55:28 +00:00 |
|
Craig Topper
|
503eef7641
|
Add test case for PR10851.
llvm-svn: 139689
|
2011-09-14 04:36:54 +00:00 |
|
Craig Topper
|
e98d8a5c84
|
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
llvm-svn: 139588
|
2011-09-13 06:54:58 +00:00 |
|
Craig Topper
|
48f2b36911
|
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
llvm-svn: 139486
|
2011-09-11 23:19:54 +00:00 |
|
Craig Topper
|
a88e356017
|
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
llvm-svn: 139485
|
2011-09-11 21:41:45 +00:00 |
|
Craig Topper
|
a948cb9058
|
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
llvm-svn: 139484
|
2011-09-11 20:23:20 +00:00 |
|
Craig Topper
|
e812f9eed5
|
Add disassembler test for Intel syntax. Tests r139353.
llvm-svn: 139356
|
2011-09-09 06:35:44 +00:00 |
|
Kevin Enderby
|
5b03f72292
|
Change X86 disassembly to print immediates values as signed by default. Special
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
|
2011-09-02 20:01:23 +00:00 |
|
Kevin Enderby
|
54e09b4799
|
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
llvm-svn: 139014
|
2011-09-02 18:03:03 +00:00 |
|
Craig Topper
|
94ce535647
|
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
llvm-svn: 138997
|
2011-09-02 04:17:54 +00:00 |
|
Craig Topper
|
4f2fba1108
|
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
llvm-svn: 138795
|
2011-08-30 07:09:35 +00:00 |
|
Kevin Enderby
|
7e2489a7c9
|
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
llvm-svn: 138771
|
2011-08-29 22:06:28 +00:00 |
|
Craig Topper
|
c66d50d1a2
|
Fix disassembling of VCVTSD2SI
llvm-svn: 138623
|
2011-08-26 04:49:29 +00:00 |
|
Craig Topper
|
76e3e0b554
|
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
llvm-svn: 138552
|
2011-08-25 07:42:00 +00:00 |
|
Craig Topper
|
e1541838f9
|
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
llvm-svn: 138551
|
2011-08-25 06:57:46 +00:00 |
|
Craig Topper
|
ba6c2a52c7
|
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
llvm-svn: 138034
|
2011-08-19 05:28:50 +00:00 |
|
Eli Friedman
|
0318036c4d
|
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
llvm-svn: 135337
|
2011-07-16 02:41:28 +00:00 |
|
Sean Callanan
|
f2f4837de3
|
Basic sanity checks to ensure that 2- and 3-byte
VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
llvm-svn: 127647
|
2011-03-15 01:32:46 +00:00 |
|
Sean Callanan
|
34770edf43
|
Fixed a bug in the enhanced disassembler that caused
it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
llvm-svn: 126302
|
2011-02-23 03:31:28 +00:00 |
|
Sean Callanan
|
c1b7775e0f
|
Added a testcase for the enhanced disassembly bug
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
llvm-svn: 126182
|
2011-02-22 02:19:18 +00:00 |
|
Rafael Espindola
|
9f9a10691a
|
Correctly disassemble truncated asm.
Patch by Richard Simth.
llvm-svn: 122962
|
2011-01-06 16:48:42 +00:00 |
|
Dale Johannesen
|
2cd8b08207
|
Segregate tests by target.
llvm-svn: 119050
|
2010-11-14 18:14:32 +00:00 |