Commit Graph

131376 Commits

Author SHA1 Message Date
Strahinja Petrovic e682b80b8b [PowerPC] fix register alignment for long double type
This patch fixes register alignment for long double type in
soft float mode. Before this patch alignment was 8 and this
patch changes it to 4.
Differential Revision: http://reviews.llvm.org/D18034

llvm-svn: 268909
2016-05-09 12:27:39 +00:00
Chris Dewhurst e3b8645a1c [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargets
This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor.

The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins.

Note: The functions are provided only for inline-assembly provision. No DAG selection is provided.

Differential Revision: http://reviews.llvm.org/D19911

llvm-svn: 268908
2016-05-09 11:55:15 +00:00
Silviu Baranga f60be28ed8 [AArch64] Implement lowering of the X constraint on AArch64
Summary:
This implements the lowering of the X constraint on
AArch64.

The default behaviour of the X constraint lowering is to
restrict it to "f". This is a problem because the "f"
constraint is not implemented on AArch64 and would be too
restrictive anyway. Therefore, the AArch64 hook will
lower this to "w" (if the operand is a floating point or
vector) or "r" otherwise.

The implementation is similar with the one added for
ARM (r267411).

This is the AArch64 side of the fix for http://llvm.org/PR26493

Reviewers: rengolin

Subscribers: aemerson, rengolin, llvm-commits, t.p.northover

Differential Revision: http://reviews.llvm.org/D19967

llvm-svn: 268907
2016-05-09 11:10:44 +00:00
Simon Pilgrim bf3a4f552e [X86][AVX512] Added masked version of combine tests
llvm-svn: 268904
2016-05-09 10:43:13 +00:00
Benjamin Kramer 2b68d15d6f Revert "[Mips] Fix use after free."
Fixes use after free but breaks tests.

This reverts commit r268901.

llvm-svn: 268902
2016-05-09 10:31:17 +00:00
Benjamin Kramer 5e2e8ddb2e [Mips] Fix use after free.
llvm-svn: 268901
2016-05-09 10:21:56 +00:00
Daniel Sanders 3d00056515 [mips][ias] R_MIPS_(GOT|HI|LO|PC)16 and R_MIPS_GPREL32 do not need symbols.
Summary:
In theory, care must be taken to ensure that pairs of R_MIPS_(GOT|HI|LO)16
make the same decision on both relocs in the reloc pair but in practice
this isn't as hard as it sounds and only limits the complexity of the
predicate used. We handle all three with the same code to ensure their
decisions always agree with each other.

Reviewers: sdardis

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19016

llvm-svn: 268900
2016-05-09 10:21:14 +00:00
Zlatko Buljan ba553a6e0a [mips][microMIPS] Implement LWP and SWP instructions
Differential Revision: http://reviews.llvm.org/D10640

llvm-svn: 268896
2016-05-09 08:07:28 +00:00
Frederic Riss 5af2c005eb [dsymutil] Fix -arch option for thumb variants.
r267249 removed the dual ARM/Thumb interface from MachOObjectFile,
simplifying llvm-dsymutil's code. This unfortunately also regressed
llvm-dsymutil's ability to select thumb slices, because the simplified
code was also dealing with the discrepency between the slice arch
(eg. armv7m) and the triple arch name (eg. thumbv7m).

llvm-svn: 268894
2016-05-09 06:01:12 +00:00
Craig Topper a5d0bf5c36 [X86] Strengthen some type contraints for floating point round and extend.
llvm-svn: 268892
2016-05-09 05:34:14 +00:00
Craig Topper a58abd1cc6 [AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result.
llvm-svn: 268891
2016-05-09 05:34:12 +00:00
Mehdi Amini dfa2392f09 ThinLTOCodeGenerator: ignore 0 values for the cache settings.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268890
2016-05-09 05:16:30 +00:00
Craig Topper 707c89c00d [AVX512] Add non-temporal store patterns for v16i32/v32i16/v64i8.
llvm-svn: 268889
2016-05-08 23:43:17 +00:00
Junmo Park 955298746d Minor code cleanups. NFC.
llvm-svn: 268888
2016-05-08 23:22:58 +00:00
Craig Topper c41320d700 [AVX512] Add missing patterns for non-temporal stores of 128/256-bit vXi8/vXi16/vXi32 when VLX is enabled. The equivalent AVX1/2 patterns are disabled by VLX.
This caused regular stores to be emitted instead.

llvm-svn: 268886
2016-05-08 23:08:45 +00:00
Craig Topper 906f397137 [AVX512] Change predicates on some vXi16/vXi8 AVX store patterns so they stay enabled unless VLX and BWI instructions are supported."
Without this we could fail instruction selection if VLX was enabled, but BWI wasn't.

llvm-svn: 268885
2016-05-08 23:08:40 +00:00
Craig Topper e5ce84a33c [AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX encoded VPXORD so all 32 registers can be used.
llvm-svn: 268884
2016-05-08 21:33:53 +00:00
Craig Topper 298b6d7493 [X86] Re-generate tests using update_llc_test_checks.py to prepare for a future commit. NFC
llvm-svn: 268883
2016-05-08 21:33:47 +00:00
Craig Topper 092794b82a Remove Windows line endings in some tests to prepare for a future commit. NFC
llvm-svn: 268882
2016-05-08 21:33:44 +00:00
Bruno Cardoso Lopes d98b3de9ef [Bitcode] Fix an unsigned integer overflow while parsing bitcode wrapper header
Specially crafted bitcode wrapper headers can cause unsigned interger
overflow and lead to crashes when wrapping around. Fix the offset check
and avoid such scenarios.

Writing a testcase for this would involve editing the binary to generate
values that trigger the overflow, since this would never happen while
generating the bitcode in regular compilation flows, so there's
currently no feasible way add one.

llvm-svn: 268881
2016-05-08 21:27:39 +00:00
Craig Topper 9d9251b86f [X86] Remove extra patterns that check for BUILD_VECTOR of all 0s. These are always canonicalized to v4i32/v8i32/v16i32 except for in SSE1 only when only v4f32 is supported.
llvm-svn: 268880
2016-05-08 20:10:20 +00:00
Simon Pilgrim 4a9d32c5ba [CostModel][X86] Extended comparison instruction cost model tests to include SSE2/SSE3/SSSE3/SSE41/SSE42 targets
llvm-svn: 268877
2016-05-08 15:24:53 +00:00
David Majnemer eac58d8f68 [X86] Promote several single precision FP libcalls on Windows
A number of libcalls don't exist in any particular lib but are, instead,
defined in math.h as inline functions (even in C mode!).  Don't rely on
their existence when lowering @llvm.{cos,sin,floor,..}.f32, promote them
instead.

N.B. We had logic to handle FREM but were missing out on a number of
others.  This change generalizes the FREM handling.

llvm-svn: 268875
2016-05-08 08:15:50 +00:00
Craig Topper d681e23336 [X86] Lower 256-bit vector all-zero constants to v8i32 even with AVX1 only. Either way a 256-bit VXORPS will be used.
llvm-svn: 268873
2016-05-08 07:10:54 +00:00
Craig Topper 3d6722910c [X86] Add patterns for 256-bit non-temporal stores when only AVX1 is supported. While there, add a predicate to the SSE2 patterns to avoid an ordering dependency.
llvm-svn: 268872
2016-05-08 07:10:50 +00:00
Craig Topper d788498411 [X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1.
llvm-svn: 268871
2016-05-08 07:10:47 +00:00
Weiming Zhao 5b5501e817 [ARM] Fix Scavenger assert due to underestimated stack size
(re-apply r268810 as it exposed an uninitialized variable in ARM MFI.
 Patch 268868 should fix that.)

Summary:
Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure.

Reviewers: rengolin

Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits

Differential Revision: http://reviews.llvm.org/D19896

llvm-svn: 268869
2016-05-08 05:11:54 +00:00
Weiming Zhao 453b79013e Fix use-of-uninitialized-value of ARMMachineFunctionInfo
Summary: Explicitly initialize ArgumentStackSize to prevent the msan failure.

Reviewers: rengolin

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D20051

llvm-svn: 268868
2016-05-08 05:04:47 +00:00
Simon Pilgrim ed39d150f5 Fix unused variable warning.
llvm-svn: 268867
2016-05-07 20:19:59 +00:00
Simon Pilgrim b6f82c449a [SelectionDAG] Added bitreverse(bitreverse(v)) --> v
Added bitreverse creation testing

llvm-svn: 268865
2016-05-07 20:12:36 +00:00
Craig Topper 6502975cf5 [X86] Fix InstAliases to not allow FARCALL32i/FARCALL16i/FARJMP32i/FARJMP16i in 64-bit mode.
llvm-svn: 268863
2016-05-07 19:25:56 +00:00
Simon Pilgrim 8ef046a8ca [X86] Added BITREVERSE constant folding and identity tests
Identity tests are currently failing - this will be fixed soon

llvm-svn: 268862
2016-05-07 19:04:00 +00:00
Simon Pilgrim 96e5307d4e [X86] Pulled out duplicate mask width calculation. NFCI.
llvm-svn: 268861
2016-05-07 18:04:24 +00:00
Simon Pilgrim 420852e8d4 [CostModel][X86] Split BSWAP/BITREVERSE cost tests from CTPOP/CTLZ/CTTZ 'bit count' cost tests
llvm-svn: 268859
2016-05-07 16:34:16 +00:00
Sanjay Patel c2751e7050 [x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons
For the sake of minimalism, this patch is x86 only, but I think that at least
PPC, ARM, AArch64, and Sparc probably want to do this too.

We might want to generalize the hook and pattern recognition for a target like
PPC that has a full assortment of negated logic ops (orc, nand).

Note that http://reviews.llvm.org/D18842 will cause this transform to trigger
more often.

For reference, this relates to:
https://llvm.org/bugs/show_bug.cgi?id=27105
https://llvm.org/bugs/show_bug.cgi?id=27202
https://llvm.org/bugs/show_bug.cgi?id=27203
https://llvm.org/bugs/show_bug.cgi?id=27328

Differential Revision: http://reviews.llvm.org/D19087

llvm-svn: 268858
2016-05-07 15:03:40 +00:00
NAKAMURA Takumi 3bf8061f1a ErrorInfoBase::message(): Don't use raw_string_ostream's buffer, Msg, before closing. Use raw_string_ostream::str() to flush the buffer.
llvm-svn: 268856
2016-05-07 08:43:11 +00:00
Xinliang David Li d55827f7b2 [PM] code refactoring -- preparation for new PM porting /NFC
llvm-svn: 268851
2016-05-07 05:39:12 +00:00
Mehdi Amini bbedb1495c Fix stripDebugInfo: was modifying "DebugLoc" attached to the intrinsic after deleting it.
Fix MSAN build.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268849
2016-05-07 05:07:47 +00:00
NAKAMURA Takumi 77edc2ef9f MipsELFObjectWriter.cpp: Activate debug printer just for +Asserts. [-Wunused-function]
llvm-svn: 268848
2016-05-07 04:51:51 +00:00
Mehdi Amini 581f0e1451 Refactor stripDebugInfo(Function) to handle intrinsic
This moves the code that handles stripping debug info intrinsic from
 StripDebugInfo(Module) to StripDebugInfo(Function). The latter is
already walking every instructions so it makes sense to do it at the
same time.
This makes also stripDebugInfo(Function) as an API more useful: it
is really dropping every debug info in the Function.
Finally the existing code is trigerring an assertion when the Module
is not fully materialized.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268847
2016-05-07 04:10:52 +00:00
Lang Hames 2a1ee0fc23 [Orc] Fix missing rename from r268845.
llvm-svn: 268846
2016-05-07 03:48:56 +00:00
Lang Hames 4821c24d08 [Orc] Rename OrcArchitectureSupport to OrcABISupport and add Win32 ABI support.
This enables lazy JITing on Windows x86-64.

Patch by David. Thanks David!

llvm-svn: 268845
2016-05-07 03:36:38 +00:00
Vitaly Buka 49bbbd8e7a Revert r268832 "Refactor stripDebugInfo(Function) to handle intrinsic"
It breaks many bots

llvm-svn: 268837
2016-05-07 02:10:59 +00:00
Sanjoy Das 987aaa1374 [ValueTracking] Hoist some computation out of a loop; NFC
There is no need to match the comparison instruction repeatedly.

llvm-svn: 268836
2016-05-07 02:08:24 +00:00
Sanjoy Das 5056e19fce Clean up comment; NFC
llvm-svn: 268835
2016-05-07 02:08:22 +00:00
Sanjoy Das 6082c1a39c Delete trailing whitespace; NFC
llvm-svn: 268834
2016-05-07 02:08:15 +00:00
Vitaly Buka e81d96be6f Revert r268810 becase it brakes msan bot.
16802==WARNING: MemorySanitizer: use-of-uninitialized-value
    lib/Target/ARM/ARMFrameLowering.cpp:1632

llvm-svn: 268833
2016-05-07 01:54:00 +00:00
Mehdi Amini 6eef08138e Refactor stripDebugInfo(Function) to handle intrinsic
This moves the code that handles stripping debug info intrinsic from
 StripDebugInfo(Module) to StripDebugInfo(Function). The latter is
already walking every instructions so it makes sense to do it at the
same time.
This makes also stripDebugInfo(Function) as an API more useful: it
is really dropping every debug info in the Function.
Finally the existing code is trigerring an assertion when the Module
is not fully materialized.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268832
2016-05-07 01:42:36 +00:00
Ahmed Bougacha 04a8fc2e37 [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
This re-applies r268760, reverted in r268794.
Fixes http://llvm.org/PR27670

The original imp-defs assertion was way overzealous: forward all
implicit operands, except imp-defs of the new super-reg def (r268787
for GR64, but also possible for GR16->GR32), or imp-uses of the new
super-reg use.
While there, mark the source use as Undef, and add an imp-use of the
old source reg: that should cover any case of dead super-regs.

At the stage the pass runs, flags are unlikely to matter anyway;
still, let's be as correct as possible.

Also add MIR tests for the various interesting cases.

Original commit message:
Codesize is less (16) or equal (8), and we avoid partial
dependencies.

Differential Revision: http://reviews.llvm.org/D19999

llvm-svn: 268831
2016-05-07 01:11:17 +00:00
Ahmed Bougacha 068ac4af39 [X86] Register and initialize the FixupBW pass.
That lets us use it in MIR tests.

llvm-svn: 268830
2016-05-07 01:11:10 +00:00