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127 Commits

Author SHA1 Message Date
Benjamin Kramer ef479ea854 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Charles Davis 74c282b5ef Add retw and lretw instructions. Also, fix Intel syntax parsing for all 
ret instructions.

llvm-svn: 154468
 2012-04-11 01:10:53 +00:00
Craig Topper 7629d63bc4 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
llvm-svn: 153935
 2012-04-03 05:20:24 +00:00
Joerg Sonnenberger 5463e66768 Fix generation of the address size override prefix. Add assertions for 
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.

llvm-svn: 153166
 2012-03-21 05:48:07 +00:00
Kevin Enderby 1ef22f33d0 Change the X86 assembler to not require a segment register on string 
instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().

llvm-svn: 152654
 2012-03-13 19:47:55 +00:00
Kevin Enderby fb3110b5d2 Added a missing error check for X86 assembly with mismatched base and index 
registers not both being 64-bit or both being 32-bit registers.

llvm-svn: 152580
 2012-03-12 21:32:09 +00:00
Kevin Enderby deed5aaa41 Add the missing call to Error when a bad X86 scale expression is parsed. 
llvm-svn: 152443
 2012-03-09 22:24:10 +00:00
NAKAMURA Takumi aebd3da46d test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets. 
llvm-svn: 152406
 2012-03-09 14:52:38 +00:00
Eli Friedman de850676e0 Fix the operand ordering on aliases for shld and shrd. PR12173, part 2. 
llvm-svn: 152136
 2012-03-06 19:58:46 +00:00
Eli Friedman a5a6d6aa8f Make aliases for shld and shrd match gas. PR12173. 
llvm-svn: 152014
 2012-03-05 04:31:54 +00:00
Kevin Enderby 6fbcd8d439 Updated the llvm-mc disassembler C API to support for the X86 target. 
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166

llvm-svn: 151267
 2012-02-23 18:18:17 +00:00
Craig Topper 66a3597a4a Add vmfunc instruction to X86 assembler and disassembler. 
llvm-svn: 150899
 2012-02-19 01:39:49 +00:00
Craig Topper ed7aa46366 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. 
llvm-svn: 150873
 2012-02-18 08:19:49 +00:00
Eli Bendersky 924f9a671d Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed. 
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.

llvm-svn: 150664
 2012-02-16 06:28:33 +00:00
Devang Patel 7cdb2ff6b5 Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. 
llvm-svn: 149291
 2012-01-30 22:47:12 +00:00
Devang Patel 9a9bb5c5db Intel syntax. Support .intel_syntax directive. 
llvm-svn: 149270
 2012-01-30 20:02:42 +00:00
Devang Patel 63fe5697f4 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] 
llvm-svn: 149142
 2012-01-27 19:48:28 +00:00
Devang Patel a410ed3ced Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. 
llvm-svn: 148864
 2012-01-24 21:43:36 +00:00
Devang Patel cf893a437e Intel syntax: Robustify parsing of memory operand's displacement experssion. 
llvm-svn: 148737
 2012-01-23 22:35:25 +00:00
Devang Patel e660fdd953 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
llvm-svn: 148721
 2012-01-23 20:20:06 +00:00
Devang Patel 880bc1644b Intel syntax: Parse segment registers. 
llvm-svn: 148712
 2012-01-23 18:31:58 +00:00
Devang Patel ce6a2ca8c8 Intel syntax: Robustify register parsing. 
llvm-svn: 148591
 2012-01-20 22:32:05 +00:00
Devang Patel d0930fff85 Intel syntax: Parse ... PTR [-8] 
llvm-svn: 148570
 2012-01-20 21:21:01 +00:00
Devang Patel f36613cb45 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. 
llvm-svn: 148569
 2012-01-20 21:14:06 +00:00
Devang Patel f83dcfd052 Post process 'and', 'sub' instructions and select better encoding, if available. 
llvm-svn: 148489
 2012-01-19 18:40:55 +00:00
Devang Patel 2529dd9e00 Intel syntax: There is no need to create unary expr for simple negative displacement. 
llvm-svn: 148486
 2012-01-19 18:15:51 +00:00
Devang Patel 4a62ff9bcb Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
llvm-svn: 148485
 2012-01-19 17:53:25 +00:00
Devang Patel de47cced25 Process instructions after match to select alternative encoding which may be more desirable. 
llvm-svn: 148431
 2012-01-18 22:42:29 +00:00
Devang Patel c9ed518792 Intel syntax: Fix parser match class to check memory operand size. 
llvm-svn: 148338
 2012-01-17 21:48:03 +00:00
Devang Patel a7143b6a2b Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
llvm-svn: 148334
 2012-01-17 21:25:10 +00:00
Devang Patel 8b39be79ad Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
llvm-svn: 148321
 2012-01-17 19:08:07 +00:00
Devang Patel a77c03be54 Intel syntax: Ignore mnemonic aliases. 
llvm-svn: 148316
 2012-01-17 18:30:45 +00:00
Devang Patel 41b9ddeb7a Intel syntax: Robustify memory operand parsing. 
llvm-svn: 148312
 2012-01-17 18:00:18 +00:00
Devang Patel 5d85276e30 Add new test. 
llvm-svn: 148128
 2012-01-13 18:45:31 +00:00
Devang Patel b04a09a515 Remove test case, as Chris suggested. 
llvm-svn: 148039
 2012-01-12 19:54:02 +00:00
Devang Patel 0014e38a8b Add test case to check intel syntax parsing. 
llvm-svn: 148034
 2012-01-12 18:40:46 +00:00
Eli Friedman 64944090ff Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
llvm-svn: 146709
 2011-12-15 23:46:18 +00:00
Jan Sjödin 7c0face455 XOP instructions and encoding tests. 
llvm-svn: 146407
 2011-12-12 19:37:49 +00:00
Jan Sjödin 9430e284a9 Support for encoding all FMA4 instructions and tablegen patterns for all 
remaining FMA4 instructions and intrinsics with tests.

llvm-svn: 145525
 2011-11-30 22:09:42 +00:00
Bruno Cardoso Lopes 0f9a1f5e6c This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

llvm-svn: 145133
 2011-11-25 19:33:42 +00:00
Benjamin Kramer 651db37352 X86: alias cqo to cqto. 
llvm-svn: 145121
 2011-11-24 12:02:46 +00:00
Rafael Espindola 300dcb8e37 Move test to the X86 directory, note the PR number and only run MC once. 
llvm-svn: 143352
 2011-10-31 17:23:09 +00:00
Kevin Enderby 49e6a0da7e Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and 
not depend on In32BitMode.  Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode.  rdar://9738584

llvm-svn: 143112
 2011-10-27 17:40:41 +00:00
Craig Topper b05d9e9bea Add X86 SARX, SHRX, and SHLX instructions. 
llvm-svn: 142779
 2011-10-23 22:18:24 +00:00
Craig Topper 980d59832a Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Craig Topper ef309c3384 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
llvm-svn: 142480
 2011-10-19 07:48:35 +00:00
Craig Topper 96fa597828 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Chris Lattner a3a0681083 Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106
 2011-10-16 04:47:35 +00:00
Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00