Commit Graph

73511 Commits

Author SHA1 Message Date
Akira Hatanaka 2e766ed2f8 Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
2011-07-07 18:57:00 +00:00
Akira Hatanaka ac4db9251b Add missing return statement.
llvm-svn: 134622
2011-07-07 18:27:36 +00:00
Devang Patel bf8cc60d1b If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example,
DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 

llvm-svn: 134620
2011-07-07 17:45:33 +00:00
Joerg Sonnenberger e0cbf7409c Recognize mipseb as alias for mips for symmetry with mipsel.
llvm-svn: 134617
2011-07-07 16:53:52 +00:00
Oscar Fuentes 32a45e5aeb Update CMake library dependencies
llvm-svn: 134616
2011-07-07 16:33:00 +00:00
Douglas Gregor cc4a55f6f2 Fix CMake build
llvm-svn: 134614
2011-07-07 15:59:22 +00:00
Cameron Zwarich 148220306f The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
2011-07-07 08:28:52 +00:00
Evan Cheng f2c2616e72 Sink feature IsThumb into MC layer.
llvm-svn: 134608
2011-07-07 08:26:46 +00:00
Evan Cheng 51dbe6e705 Feature bits are 64-bits.
llvm-svn: 134607
2011-07-07 07:45:49 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Chris Lattner 54677c15f3 type can be null
llvm-svn: 134601
2011-07-07 05:29:18 +00:00
Chris Lattner cdfcc2dee6 use a more efficient check for 'is metadata'
llvm-svn: 134599
2011-07-07 05:12:37 +00:00
Bill Wendling 667be58220 Use ArrayRef instead of a std::vector&.
llvm-svn: 134595
2011-07-07 04:42:01 +00:00
Lang Hames 5a00499e87 Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.

X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)

Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).

Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.

llvm-svn: 134592
2011-07-07 04:31:51 +00:00
Evan Cheng 8b2bda09a5 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
llvm-svn: 134590
2011-07-07 03:55:05 +00:00
Bill Wendling b6adf46f62 Add a target hook to encode the compact unwind information.
llvm-svn: 134577
2011-07-07 00:54:13 +00:00
Jim Grosbach 4c08a9f838 Add isCodeGenOnly value to the CodeGenInstruction class.
So users of a CGI don't have to look up the value directly from the original
Record; just like the rest of the convenience values in the class.

llvm-svn: 134576
2011-07-07 00:48:02 +00:00
Lang Hames 2bbdc0bcda Added a testcase for PR10220.
llvm-svn: 134573
2011-07-07 00:36:02 +00:00
Devang Patel b7a328ed27 Add DEBUG messages.
llvm-svn: 134572
2011-07-07 00:14:27 +00:00
Evan Cheng 2bd65363a8 Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
llvm-svn: 134569
2011-07-07 00:08:19 +00:00
Devang Patel 41e97da74f Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion.
llvm-svn: 134568
2011-07-07 00:05:58 +00:00
Jakub Staszak a11f7ecbf8 Fix a bug in the "expect" intrinsic lowering.
llvm-svn: 134566
2011-07-06 23:50:16 +00:00
Eli Friedman bf007364bf When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF).
Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.

<rdar://problem/9716278>

llvm-svn: 134565
2011-07-06 23:41:48 +00:00
Jim Grosbach fdc02c1b0d Typo.
llvm-svn: 134563
2011-07-06 23:38:13 +00:00
Devang Patel 92ca8fc927 Remove dead code.
llvm-svn: 134561
2011-07-06 23:26:18 +00:00
Devang Patel 338e43268c Typo.
llvm-svn: 134559
2011-07-06 23:09:51 +00:00
Bill Wendling 7ed5625082 Clean up the #includes.
llvm-svn: 134557
2011-07-06 22:52:32 +00:00
Eric Christopher ea336c797c Grammar and 80-col.
llvm-svn: 134555
2011-07-06 22:41:18 +00:00
Owen Anderson 145a260f75 Fix a subtle issue in SmallVector. The following code did not work as expected:
vec.insert(vec.begin(), vec[3]);
The issue was that vec[3] returns a reference into the vector, which is invalidated when insert() memmove's the elements down to make space.  The method needs to specifically detect and handle this case to correctly match std::vector's semantics.

Thanks to Howard Hinnant for clarifying the correct behavior, and explaining how std::vector solves this problem.

llvm-svn: 134554
2011-07-06 22:36:59 +00:00
Devang Patel c6ee9181d0 Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to one alloca.
llvm-svn: 134549
2011-07-06 22:06:11 +00:00
Evan Cheng 928ce72bcd Add ARM MC registry routines.
llvm-svn: 134547
2011-07-06 22:02:34 +00:00
Evan Cheng 3ddfbd325d Rename files for consistency.
llvm-svn: 134546
2011-07-06 22:01:53 +00:00
Nick Lewycky b6b067c225 Add ImmutableList::contains(). Patch by Rui Paulo!
llvm-svn: 134545
2011-07-06 21:59:48 +00:00
Jim Grosbach 7c301ea093 Mark ARM pseudo-instructions as isPseudo.
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540
2011-07-06 21:35:46 +00:00
Jim Grosbach f3fd36e0f5 Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.

llvm-svn: 134539
2011-07-06 21:33:38 +00:00
Devang Patel a3cbf52a57 Simplify. Consolidate dbg.declare handling in AllocaPromoter.
llvm-svn: 134538
2011-07-06 21:09:55 +00:00
Andrew Trick 9f8c2853ca indvars -disable-iv-rewrite: ExprToMap lives in Pass data, so be more
careful about referencing values.

llvm-svn: 134537
2011-07-06 21:07:10 +00:00
Jim Grosbach 4db363af7c Remove un-used encoding info from Pseudo MLAv5.
Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533
2011-07-06 20:57:35 +00:00
Eli Friedman 499647bfc3 Fix missing triple support for RTEMS target.
llvm-svn: 134532
2011-07-06 20:56:26 +00:00
Andrew Trick 3239055dee indvars -disable-iv-rewrite: Added SimplifyCongruentIVs.
llvm-svn: 134530
2011-07-06 20:50:43 +00:00
Eli Friedman 402339b875 Remove some unnecessary includes.
llvm-svn: 134528
2011-07-06 20:48:27 +00:00
Bill Wendling 5ace8edfd6 Constify getCompactUnwindRegNum.
llvm-svn: 134527
2011-07-06 20:33:48 +00:00
Evan Cheng ab37af9af3 createMCInstPrinter doesn't need TargetMachine anymore.
llvm-svn: 134525
2011-07-06 19:45:42 +00:00
Tobias Grosser a3928f5084 LICM: Remove trailing white spaces
llvm-svn: 134521
2011-07-06 19:20:02 +00:00
Tobias Grosser 4a5d9a9c20 LICM: Do not loose alignment on promotion
The promotion code lost any alignment information, when hoisting loads and
stores out of the loop. This lead to incorrect aligned memory accesses. We now
use the largest alignment we can prove to be correct.

llvm-svn: 134520
2011-07-06 19:19:55 +00:00
Jakub Staszak dce4dffc84 Add documenation about "branch_weight" metadata and __builtin_expect instruction
llvm-svn: 134517
2011-07-06 18:31:02 +00:00
Jakub Staszak 3f158fdf6e Introduce "expect" intrinsic instructions.
llvm-svn: 134516
2011-07-06 18:22:43 +00:00
Kevin Enderby 6aac575c9f Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501.
llvm-svn: 134511
2011-07-06 17:55:20 +00:00
Kevin Enderby 6ee1d2bd78 Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.

llvm-svn: 134501
2011-07-06 17:23:46 +00:00
David Greene afb9ba7dad Allow tagless builds and fix debug build configuration.
llvm-svn: 134498
2011-07-06 16:54:14 +00:00