ea2d52d867
Split the impl of CodeGenInstruction out to its own .cpp file, add a getName() accessor.
...
llvm-svn: 45645
2008-01-06 01:35:39 +00:00
8cab021ca2
change getQualifiedName to be a global function.
...
Split the pattern parsing code out from the dag isel emitter into it's own file.
No functionality change.
llvm-svn: 45632
2008-01-05 22:25:12 +00:00
8adcd9f32e
remove attributions from utils.
...
llvm-svn: 45419
2007-12-29 20:37:13 +00:00
cb77f04e1f
Add flags to indicate that there are "never" side effects or that there "may be"
...
side effects for machine instructions.
llvm-svn: 45022
2007-12-14 01:48:59 +00:00
687567bca5
Oops. Forgot these.
...
llvm-svn: 44969
2007-12-13 00:42:35 +00:00
933b5b7e62
Add a flag for indirect branch instructions.
...
Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
25a00a63eb
Add sqrt and powi intrinsics for long double.
...
llvm-svn: 42423
2007-09-28 01:08:20 +00:00
f73fb6261b
Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
...
between two registers in the specific class.
llvm-svn: 42123
2007-09-19 01:35:01 +00:00
febf946ea7
Add MVT::fAny for overloading intrinsics on floating-point types.
...
llvm-svn: 41128
2007-08-16 21:57:19 +00:00
7132e00de7
This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
...
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.
llvm-svn: 40807
2007-08-04 01:51:18 +00:00
cde0ee5221
Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
...
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
c9ea29456a
Teach TableGen about the new vector types.
...
llvm-svn: 40513
2007-07-26 06:41:18 +00:00
869852b03e
No need for noResults anymore.
...
llvm-svn: 40075
2007-07-20 00:21:23 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
10835d9c67
Eliminate an unused parameter.
...
llvm-svn: 39828
2007-07-13 20:16:50 +00:00
6e3c705d74
Try committing again. Add OptionalDefOperand. Remove clobbersPred.
...
llvm-svn: 38498
2007-07-10 18:05:01 +00:00
9835db562f
ImmutablePredicateOperand is no more.
...
llvm-svn: 37963
2007-07-06 23:23:38 +00:00
e32e7fb40d
Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.
...
llvm-svn: 37899
2007-07-05 07:19:29 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
...
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
f274efef9f
Add support to tablegen for specifying subregister classes on a per register class basis.
...
llvm-svn: 37572
2007-06-13 22:20:15 +00:00
452a818c6a
Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.
...
llvm-svn: 37465
2007-06-06 10:14:55 +00:00
a23ef8a8f2
Remove the operator<< for MVT::ValueType in preparation for MVT::ValueType
...
being changed from an enum to an integer type, which can't have a custom
operator<< overload.
llvm-svn: 37412
2007-06-04 16:11:03 +00:00
b99726d7a0
Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand.
...
llvm-svn: 37116
2007-05-16 20:45:24 +00:00
e67d0c226d
For PR1297:
...
Implement code generation for overloaded intrinsic functions. The basic
difference is that "actual" argument types must be provided when
constructing intrinsic names and types. Also, for recognition, only the
prefix is examined. If it matches, the suffix is assumed to match. The
suffix is checked by the Verifier, however.
llvm-svn: 35539
2007-04-01 07:20:02 +00:00
98d2104c6f
Add support for the v1i64 type. This makes better code for this:
...
#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
llvm-svn: 35351
2007-03-26 07:53:08 +00:00
9d7d130835
Recognize target instruction flag 'isReMaterializable'.
...
llvm-svn: 35159
2007-03-19 06:20:37 +00:00
cbebe4600f
reapply
...
llvm-svn: 34697
2007-02-27 22:08:27 +00:00
116ec30e4f
Backing out
...
CodeGenTarget.cpp updated: 1.82 -> 1.83
Record.cpp updated: 1.55 -> 1.56
Record.h updated: 1.59 -> 1.60
TableGen.cpp updated: 1.47 -> 1.48
It's missing CallingConvEmitter.h
llvm-svn: 34693
2007-02-27 21:44:08 +00:00
fa024e1ad1
initial support for calling convention generation, still unfinished.
...
llvm-svn: 34682
2007-02-27 20:43:37 +00:00
214c582002
Files missing from LABEL check in.
...
llvm-svn: 33539
2007-01-26 17:29:20 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
8e94078483
Match TargetInstrInfo changes.
...
llvm-svn: 32107
2006-12-01 22:57:41 +00:00
78a403f90e
Remove the isTwoAddress property from the CodeGenInstruction class. It should
...
not be used for anything other than backwards compat constraint handling.
Add support for a new DisableEncoding property which contains a list of
registers that should not be encoded by the generated code emitter. Convert
the codeemitter generator to use this, fixing some PPC JIT regressions.
llvm-svn: 31769
2006-11-15 23:23:02 +00:00
c94f214d22
ADd support for adding constraints to suboperands
...
llvm-svn: 31748
2006-11-15 02:38:17 +00:00
ba7b3673f9
allow ptr_rc to explicitly appear in an instructions operand list, it doesn't
...
have to be a subpart of a complex operand.
llvm-svn: 31618
2006-11-10 02:01:40 +00:00
5d14eac21d
emit TIED_TO correctly
...
llvm-svn: 31484
2006-11-07 01:27:55 +00:00
33f5a51020
simplify the way operand flags and constraints are handled, making it easier
...
to extend.
llvm-svn: 31481
2006-11-06 23:49:51 +00:00
8a9c91de33
recognize ppc's blr instruction as predicated
...
llvm-svn: 31480
2006-11-06 21:44:54 +00:00
3cb5bf721c
Clean up some code.
...
llvm-svn: 31451
2006-11-04 09:40:23 +00:00
7982de167f
eliminate need for the NumMIOperands field in Operand.
...
llvm-svn: 31432
2006-11-03 23:45:17 +00:00
3557a39494
Tied-to constraint must be op_with_larger_idx = op_with_smaller_idx or else throw an exception.
...
llvm-svn: 31361
2006-11-01 23:03:11 +00:00
ac79c7c4c0
Add operand constraints to TargetInstrInfo.
...
llvm-svn: 31333
2006-11-01 00:27:05 +00:00
2022c79d7f
Added properties such as SDNPHasChain to ComplexPattern.
...
llvm-svn: 30890
2006-10-11 21:02:01 +00:00
5d038cf802
Allow more use of iPTR in patterns.
...
llvm-svn: 28790
2006-06-15 00:16:37 +00:00
fe72285033
Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
...
llvm-svn: 28376
2006-05-18 00:08:46 +00:00
318a68e1ee
Typo
...
llvm-svn: 28366
2006-05-17 20:55:51 +00:00
f5ef47fe74
Remove PointerType from target definition. Use abstract type MVT::iPTR to
...
represent pointer type.
llvm-svn: 28363
2006-05-17 20:37:59 +00:00
d985d66781
Allow patterns to refer to physical registers that belong to multiple
...
register classes.
llvm-svn: 28323
2006-05-16 07:05:30 +00:00
Chris Lattner