dd0821e7ff
Start handling more global variables.
...
llvm-svn: 116401
2010-10-13 09:11:46 +00:00
4c71c117d1
RegionInfo: Fix trivial error that slipped in last minute.
...
llvm-svn: 116400
2010-10-13 08:00:53 +00:00
fe92a9384e
RegionInfo: Update RegionInfo after a BB was split.
...
llvm-svn: 116398
2010-10-13 05:54:13 +00:00
a8677226ab
RegioInfo: Add getExpandedRegion().
...
getExpandedRegion() enables us to create non canonical regions. Those regions
can be used to define the largerst region, that fullfills a certain property.
llvm-svn: 116397
2010-10-13 05:54:11 +00:00
648594c920
RegionInfo: Allow to update exit and entry of a region.
...
llvm-svn: 116396
2010-10-13 05:54:10 +00:00
bf984fd78e
RegionInfo: Enhance addSubregion.
...
llvm-svn: 116395
2010-10-13 05:54:09 +00:00
8352ce5f8d
RegionInfo: Allow to set the parent region of a basic block.
...
llvm-svn: 116394
2010-10-13 05:54:07 +00:00
c2240adcc7
Fix PR8313 by changing ValueToValueMap use a TrackingVH.
...
llvm-svn: 116390
2010-10-13 02:08:17 +00:00
3912158997
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
...
llvm-svn: 116389
2010-10-13 01:54:21 +00:00
229e38f0fe
Be more consistent in using ValueToValueMapTy.
...
llvm-svn: 116387
2010-10-13 01:36:30 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
e910b9d9cd
RegionInfo: Free the RegionNodes in cache.
...
Contributed by: ether
llvm-svn: 116380
2010-10-13 00:07:59 +00:00
f9ca535495
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
efd5369749
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
d565b44a98
Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.
...
llvm-svn: 116368
2010-10-12 23:19:28 +00:00
12e493ace4
Move the ARM so_imm encoding into a custom operand encoder and remove the
...
explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
42200bcaea
Refactor some of the encoding logic into a base class. This keeps us from having
...
to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
llvm-svn: 116362
2010-10-12 23:06:54 +00:00
d9d31dafda
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
...
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
646a506724
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
98c29d732d
Split out the "size" field from the encoding. The newer documentation has it as
...
a separate bit in the coding.
llvm-svn: 116347
2010-10-12 22:03:19 +00:00
22e051eef0
Fix thinko in arm fast isel alloca rewrite.
...
llvm-svn: 116339
2010-10-12 21:23:43 +00:00
576640f0e3
Encoding for ARM-mode VADD.F32 instruction.
...
llvm-svn: 116338
2010-10-12 21:22:40 +00:00
8ac477ffb5
Begin adding static dependence information to passes, which will allow us to
...
perform initialization without static constructors AND without explicit initialization
by the client. For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve. I hope to be able to relax
the latter requirement in the future.
llvm-svn: 116334
2010-10-12 19:48:12 +00:00
604e142844
Combine these together - should probably have some text associated
...
that says what why what we just asserted is wrong.
llvm-svn: 116333
2010-10-12 19:44:17 +00:00
eb7b91d417
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
...
llvm-svn: 116323
2010-10-12 18:18:03 +00:00
0e57a9f7a9
Add MOVi ARM encoding.
...
llvm-svn: 116321
2010-10-12 18:09:12 +00:00
395a898b2b
Initial va_arg support for x86-64. Patch by David Meyer!
...
llvm-svn: 116319
2010-10-12 18:00:49 +00:00
feeae27ad9
Nuke unused wrapper function.
...
llvm-svn: 116318
2010-10-12 17:53:25 +00:00
aec745326a
Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
...
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.
The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.
llvm-svn: 116314
2010-10-12 17:15:00 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
dd6eb5b5a1
PR8359: The ARM backend may end up allocating registers D16 to D31 when
...
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
7cd5cda6bb
Rework alloca handling so that we can load or store from casted
...
address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
db3bcc9910
Handle a wider arrangement of loads.
...
llvm-svn: 116284
2010-10-12 00:43:21 +00:00
cb85497ddf
Delete a redundant check.
...
llvm-svn: 116280
2010-10-12 00:19:24 +00:00
060d5ba248
More SmallVectorImpls.
...
llvm-svn: 116279
2010-10-12 00:15:27 +00:00
c450d2caa5
Shrink a SmallVector with a known maximum size.
...
llvm-svn: 116278
2010-10-12 00:13:43 +00:00
c8da21b04c
Constify.
...
llvm-svn: 116277
2010-10-12 00:12:29 +00:00
7224bcef8f
Use SmallVectorImpl in a bunch of places.
...
llvm-svn: 116276
2010-10-12 00:11:18 +00:00
e790afcbe1
More ARM scheduling itinerary fixes.
...
llvm-svn: 116266
2010-10-11 23:41:41 +00:00
a8d3a7f93d
Support AA chaining.
...
llvm-svn: 116264
2010-10-11 23:39:34 +00:00
844dd0ad00
Fix the pass manager's search order for immutable passes, and make it
...
stop searching when it has found a match.
llvm-svn: 116262
2010-10-11 23:19:01 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
109ff296c8
Second set of ARM/MC/ELF changes.
...
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
94ad008beb
Proper VST scheduling itineraries.
...
llvm-svn: 116251
2010-10-11 22:03:18 +00:00
d42340ecfd
Use a sane mechanism for that assert.
...
llvm-svn: 116249
2010-10-11 22:01:22 +00:00
57feeed92f
Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis.
...
This helps hiding the LiveRange class which really should be private.
llvm-svn: 116244
2010-10-11 21:45:03 +00:00
72b91c1765
We're not going to handle dynamic allocas anywhere else.
...
llvm-svn: 116240
2010-10-11 21:37:35 +00:00
fe2a89683a
Change explicit search Apple specific code to only reference __eprintf on x86.
...
llvm-svn: 116239
2010-10-11 21:34:24 +00:00
71ef1af66b
Make sure that the call stack adjustments have default operands. Also
...
leave custom lowerings for later.
Fixes some nightly tests.
llvm-svn: 116232
2010-10-11 21:20:02 +00:00
6c4353ecee
PowerPC varargs functions store live-in registers on the stack. Make sure we use
...
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
llvm-svn: 116222
2010-10-11 20:43:09 +00:00
e2a0b6841a
Found a bug turning this on by default. Disable again for now.
...
llvm-svn: 116220
2010-10-11 20:26:21 +00:00
46cc854e5e
Fix help text.
...
llvm-svn: 116218
2010-10-11 20:15:02 +00:00
5501b7e805
Change flag from Enable to Disable since we're enabled by default.
...
Also don't use fast-isel on non-darwin since it's untested.
llvm-svn: 116217
2010-10-11 20:05:22 +00:00
e01c9001c9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
...
llvm-svn: 116214
2010-10-11 19:02:04 +00:00
5476a274c8
More binary encoding stuff, taking advantage of the new "by name" operand
...
matching in tblgen to do the predicate operand.
llvm-svn: 116213
2010-10-11 18:51:51 +00:00
2276e87a65
Turn on arm fast isel by default.
...
llvm-svn: 116212
2010-10-11 18:48:18 +00:00
2f6531eb8c
Properly handle reloading and spilling around partial redefines in
...
LocalRewriter.
This is a bit of a hack that adds an implicit use operand to model the
read-modify-write nature of a partial redef. Uses and defs are rewritten in
separate passes, and a single operand would never be processed twice.
<rdar://problem/8518892>
llvm-svn: 116210
2010-10-11 18:10:36 +00:00
0f5bfd27a3
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
...
llvm-svn: 116201
2010-10-11 11:36:19 +00:00
e1bcb43bb9
Copy and pasteo.
...
llvm-svn: 116198
2010-10-11 08:40:05 +00:00
7ac602bc8e
Whitespace cleanup in ARM fast isel.
...
llvm-svn: 116197
2010-10-11 08:38:55 +00:00
eae1b38550
Add srem libcall support to ARM fast isel.
...
llvm-svn: 116196
2010-10-11 08:37:26 +00:00
e11017c19e
Add i8 sdiv support for ARM fast isel.
...
llvm-svn: 116195
2010-10-11 08:31:54 +00:00
511aa31965
Implement select handling for ARM fast-isel.
...
llvm-svn: 116194
2010-10-11 08:27:59 +00:00
1ef5e84c31
Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
...
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.
llvm-svn: 116190
2010-10-11 05:44:40 +00:00
8dedb62019
X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.
...
llvm-svn: 116188
2010-10-11 05:29:15 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
...
llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
...
llvm-svn: 116174
2010-10-10 22:04:34 +00:00
bee1f7f5ba
Fix Whitespace.
...
llvm-svn: 116173
2010-10-10 22:04:20 +00:00
eb313a46fc
fix the default va_arg expansion (in the realignment case) to not implicitly
...
truncate the stack pointer to 32-bits on a 64-bit machine.
llvm-svn: 116169
2010-10-10 18:36:26 +00:00
d10babfd65
fix the expansion of va_arg instruction on PPC to know the arg
...
alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
llvm-svn: 116168
2010-10-10 18:34:00 +00:00
b8d7efe785
Now using a variant of the existing inlining heuristics to decide whether to create a given specialization of a function in PartialSpecialization. If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization.
...
llvm-svn: 116158
2010-10-09 22:06:36 +00:00
d84bb168cc
Silence compiler warning.
...
llvm-svn: 116156
2010-10-09 16:36:44 +00:00
a6a984bd96
MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
...
llvm-svn: 116155
2010-10-09 16:04:45 +00:00
86bbd71088
MC-COFF: Implement InitSections. Fixes PR8335.
...
llvm-svn: 116151
2010-10-09 15:44:27 +00:00
c8dbdfd4ba
MC-COFF: Add COFFAsmParser. Completes PR8343.
...
llvm-svn: 116150
2010-10-09 11:01:07 +00:00
530ce85b3e
Fix Whitespace.
...
llvm-svn: 116149
2010-10-09 11:00:50 +00:00
be52c62a6d
MC-COFF: Assert on non-coff sections.
...
llvm-svn: 116148
2010-10-09 11:00:37 +00:00
d7a404d85f
Add VLD4 scheduling itineraries.
...
llvm-svn: 116143
2010-10-09 04:07:58 +00:00
3d89823102
MC: Move ParseDirectiveELFType into ELFAsmParser. COFF uses .type for something else.
...
llvm-svn: 116142
2010-10-09 03:47:55 +00:00
a762400bed
Finish vld3 and vld4.
...
llvm-svn: 116140
2010-10-09 01:45:34 +00:00
4187f4942e
Complete vld2 instruction itineries.
...
llvm-svn: 116136
2010-10-09 01:26:12 +00:00
1c7fa43e6f
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
...
llvm-svn: 116135
2010-10-09 01:15:04 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
59ebe44049
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
c951cfe6a0
add jit support for the new psuedo instructions I added for
...
the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
llvm-svn: 116125
2010-10-08 23:59:27 +00:00
8eeb5013cd
machine a mutable machineinstr down into emitInstruction.
...
llvm-svn: 116124
2010-10-08 23:54:01 +00:00
548587c31c
Fix the store part of this as well. Fixes smg2000.
...
llvm-svn: 116123
2010-10-08 23:52:16 +00:00
959fcc6c63
Rename SplitEditor::rewrite to finish() and break it out into a couple of new
...
functions: computeRemainder and rewrite.
When the remainder breaks up into multiple components, remember to rewrite those
uses as well.
llvm-svn: 116121
2010-10-08 23:42:21 +00:00
df2aae0c5a
Avoid compiler warning: comparison between signed and unsigned integer.
...
llvm-svn: 116119
2010-10-08 23:01:57 +00:00
b1b0ef7d03
Extract method ProcessUses from LocalRewriter::RewriteMBB. Both parent and child
...
are still way too long, but it's a start.
No functional change intended.
llvm-svn: 116116
2010-10-08 22:14:41 +00:00
fc3642b205
Do not check that the bodies of two defs of same linkonce global are the same.
...
Such a check does not make any sense in presense of inlining and other compiler-dependent stuff.
This should fix bunch of warnings on mingw32.
llvm-svn: 116113
2010-10-08 21:50:04 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
05cae8326d
Classify value numbers into connected components in linear time.
...
llvm-svn: 116105
2010-10-08 21:19:28 +00:00
af8b4871a8
Call InitSections in llc and clang so that the binaries produced by them
...
are easier to diff with those produced by llvm-mc.
llvm-svn: 116095
2010-10-08 19:37:38 +00:00
Eric Christopher