20d103e74e
Remove unused accessor.
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llvm-svn: 116580
2010-10-15 16:06:40 +00:00
fbcf0db7ee
Refactor code a bit and avoid creating unnecessary entries in the string
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map.
llvm-svn: 116579
2010-10-15 15:39:06 +00:00
3b1db392fc
Remove unused ARMISD::AND selection DAG node.
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llvm-svn: 116566
2010-10-15 04:34:40 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
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have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
118c4238ff
Encoding info for extension instructions.
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llvm-svn: 116560
2010-10-15 02:29:58 +00:00
3f1f7b67e3
Eliminate curli from SplitEditor. Use the LiveRangeEdit reference instead.
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llvm-svn: 116547
2010-10-15 00:34:01 +00:00
0f3e98ce2e
Move stack slot assignments into LiveRangeEdit.
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All registers created during splitting or spilling are assigned to the same
stack slot as the parent register.
When splitting or rematting, we may not spill at all. In that case the stack
slot is still assigned, but it will be dead.
llvm-svn: 116546
2010-10-15 00:16:55 +00:00
72911e49fa
Create a new LiveRangeEdit class to keep track of the new registers created when
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splitting or spillling, and to help with rematerialization.
Use LiveRangeEdit in InlineSpiller and SplitKit. This will eventually make it
possible to share remat code between InlineSpiller and SplitKit.
llvm-svn: 116543
2010-10-14 23:49:52 +00:00
19c6cb978b
Add missing Rd encoding for MOVs instruction.
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llvm-svn: 116537
2010-10-14 23:28:31 +00:00
8b6a9c1574
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
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and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
31a01ee3cb
Tolerate a null parent pointer.
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llvm-svn: 116533
2010-10-14 22:55:57 +00:00
062749cb25
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
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pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
a3037c3abd
Always use binary mode for output stream. This is important to prevent unwanted end of line conversion on Windows. Should not affect Unix where O_BINARY is not defined. This fix /clang/test/lexer/preamble.c XFAIL on WIN32.
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llvm-svn: 116509
2010-10-14 20:30:58 +00:00
eafcb27ded
MOVi16 and MOVT ARM mode encodings.
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llvm-svn: 116498
2010-10-14 18:54:27 +00:00
f11318018a
Only split around a loop if the live range has uses outside the loop periphery.
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Before we would also split around a loop if any peripheral block had multiple
uses. This could cause repeated splitting when splitting a different live range
would insert uses into the periphery.
Now -spiller=inline passes the nightly test suite again.
llvm-svn: 116494
2010-10-14 18:26:45 +00:00
8229153629
Simplify encoding information and add 'dst' operand info for TAILJMP.
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llvm-svn: 116488
2010-10-14 17:24:28 +00:00
bee6e9f8e0
Remove some code duplication.
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llvm-svn: 116484
2010-10-14 16:34:44 +00:00
5816ccd4b5
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
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creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
llvm-svn: 116480
2010-10-14 15:54:46 +00:00
ffe32e1137
When building shared libraries, link to required system libraries.
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PR 8375
llvm-svn: 116479
2010-10-14 15:54:41 +00:00
21d0c173f4
Handle more complex GEP based loads and add a few TODOs to deal with
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GEP + alloca.
llvm-svn: 116474
2010-10-14 09:29:41 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
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here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
0441c6cba0
Add encoding for 'fmstat'.
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llvm-svn: 116466
2010-10-14 01:19:34 +00:00
d62719c3fa
Register pressure and instruction latency aware machine LICM. Work in progress.
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llvm-svn: 116465
2010-10-14 01:16:09 +00:00
0825f3e441
- Add encodings for multiply add/subtract instructions in all their glory.
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- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
b9681ad442
fix a bug I introduced, no idea how this didn't repro right.
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llvm-svn: 116462
2010-10-14 00:30:00 +00:00
1f2b4bdb22
Regenerate. No functional change, just cleanup.
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llvm-svn: 116459
2010-10-14 00:15:18 +00:00
698661c741
add uadd_ov/usub_ov to apint, consolidate constant folding
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logic to use the new APInt methods. Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold
which comes from "clang -ftrapv", originally brought to my attention from PR8221.
llvm-svn: 116457
2010-10-14 00:05:07 +00:00
2c819b0358
constify these methods.
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llvm-svn: 116455
2010-10-13 23:54:10 +00:00
d100ed858e
Detabify and clean up 80 column violations.
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llvm-svn: 116454
2010-10-13 23:47:11 +00:00
79bdd88fa4
add a few operations for signed operations that also
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return an overflow flag.
llvm-svn: 116452
2010-10-13 23:46:33 +00:00
340cd5174b
A few 80 column fixes.
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llvm-svn: 116451
2010-10-13 23:34:31 +00:00
b9386558a7
trailing whitespace
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llvm-svn: 116450
2010-10-13 23:12:26 +00:00
348013f829
Add a FIXME.
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llvm-svn: 116449
2010-10-13 22:55:33 +00:00
0708e74a95
Add operand encoding bits for SMC and SVC in ARM mode.
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llvm-svn: 116447
2010-10-13 22:38:23 +00:00
16db3287c0
More encoding cleanup. Also add register Rd operands for indirect branches.
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llvm-svn: 116444
2010-10-13 22:09:34 +00:00
071cee0c81
CallGraphSCC passes implicity require CallGraph analysis.
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llvm-svn: 116443
2010-10-13 22:00:45 +00:00
c266a36625
Analysis groups need to initialize their default implementations.
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llvm-svn: 116441
2010-10-13 21:49:58 +00:00
2a4d99ab62
Simplify some ARM encoding information.
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llvm-svn: 116440
2010-10-13 21:48:54 +00:00
ef83e21b57
Update comment.
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llvm-svn: 116438
2010-10-13 21:41:51 +00:00
9874b7de58
Add a FIXME. The ADR instruction is a bit odd.
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llvm-svn: 116437
2010-10-13 21:32:30 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
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and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
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llvm-svn: 116431
2010-10-13 20:58:46 +00:00
fb07ef19cc
Add a FIXME.
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llvm-svn: 116428
2010-10-13 20:38:04 +00:00
efc066829b
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
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wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
llvm-svn: 116427
2010-10-13 20:30:55 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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llvm-svn: 116421
2010-10-13 19:56:10 +00:00
142e3cbb26
Fix encoding for compares. No Rd register.
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llvm-svn: 116414
2010-10-13 18:05:25 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
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llvm-svn: 116412
2010-10-13 18:00:52 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
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immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
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8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
4b0986b6c1
Add Region::isTopLevelRegion().
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llvm-svn: 116402
2010-10-13 11:02:44 +00:00
Jakob Stoklund Olesen