cf20cbec49
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.
...
llvm-svn: 95999
2010-02-12 18:55:33 +00:00
905a2d7727
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2,
...
MRRC, MRRc2. For disassembly only.
llvm-svn: 95955
2010-02-12 01:44:23 +00:00
af88c0a84d
Added LDRT/LDRBT/STRT/STRBT for disassembly only.
...
llvm-svn: 95916
2010-02-11 20:31:08 +00:00
f40b8e03fb
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
...
llvm-svn: 95884
2010-02-11 18:12:29 +00:00
9c13dfb5dd
Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21
...
as the "Permanently UNDEFINED" instruction.
llvm-svn: 95873
2010-02-11 17:14:31 +00:00
c7e14704d0
Added NOP, DBG, SVC to the instruction table for disassembly purpose.
...
llvm-svn: 95784
2010-02-10 18:02:25 +00:00
a570d05228
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
5b66b31774
MOVi16 should also be marked as a UnaryDP instruction, i.e., it doesn't have a
...
Rn operand.
llvm-svn: 95025
2010-02-01 23:06:04 +00:00
b3562f7cf6
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder.
...
llvm-svn: 94955
2010-01-31 11:22:28 +00:00
267430f74d
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
...
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
llvm-svn: 94119
2010-01-22 00:08:13 +00:00
6c0fb92c03
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
...
llvm-svn: 93829
2010-01-19 00:44:15 +00:00
8546ec9c14
Patch by David Conrad:
...
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
llvm-svn: 93758
2010-01-18 19:58:49 +00:00
ea6f91ff64
Change SelectCode's argument from SDValue to SDNode *, to make it more
...
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
2010-01-05 01:24:18 +00:00
69461f50c1
Mark STREX* as earlyclobber for the success result register.
...
llvm-svn: 91555
2009-12-16 19:44:06 +00:00
bee6f16fed
Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
...
between BR_JTr and STREXD.
llvm-svn: 91339
2009-12-14 21:51:34 +00:00
3974a80307
v6 sync insn copy/paste error
...
llvm-svn: 91333
2009-12-14 21:33:32 +00:00
3c4f04112a
Add ARMv6 memory and sync barrier instructions
...
llvm-svn: 91329
2009-12-14 21:24:16 +00:00
acba3b0ae2
Fixed encoding bits typo of ldrexd/strexd.
...
llvm-svn: 91327
2009-12-14 21:01:46 +00:00
fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
...
llvm-svn: 91313
2009-12-14 19:24:11 +00:00
3cdb555e0f
whitespace
...
llvm-svn: 91307
2009-12-14 18:36:32 +00:00
5e0d2a2df6
ARM memory barrier instructions are not predicable
...
llvm-svn: 91305
2009-12-14 18:31:20 +00:00
9d6410d040
add ldrexd/strexd instructions
...
llvm-svn: 91284
2009-12-14 17:02:55 +00:00
8f9a3ac12c
Framework for atomic binary operations. The emitter for the pseudo instructions
...
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
llvm-svn: 91200
2009-12-12 01:40:06 +00:00
22a4ea8690
memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
...
llvm-svn: 91150
2009-12-11 20:29:53 +00:00
afdddaed55
Update properties.
...
llvm-svn: 91140
2009-12-11 18:52:41 +00:00
5c4e99fca6
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
...
llvm-svn: 91090
2009-12-11 01:42:04 +00:00
fed78ccfb5
Add instruction encoding for DMB/DSB
...
llvm-svn: 91053
2009-12-10 18:35:32 +00:00
53e8854443
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
...
llvm-svn: 91003
2009-12-10 00:11:09 +00:00
c168a52627
Fix some more ARM unified syntax warnings.
...
llvm-svn: 90141
2009-11-30 17:47:19 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
de5dea869f
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
...
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
...
llvm-svn: 89694
2009-11-23 20:35:53 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
9dea05d724
Fix a few places that were missed when we converted to unified syntax.
...
llvm-svn: 89214
2009-11-18 18:10:35 +00:00
14b25eb87b
Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to
...
distinguish between them and the more generic instructions (add, mov, and ldr).
llvm-svn: 89108
2009-11-17 17:17:50 +00:00
18183b6d8e
Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to
...
0b1110 (ALways). This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.
llvm-svn: 89000
2009-11-16 23:57:56 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
...
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
d1d002a6fe
Support alignment specifier for NEON vld/vst instructions
...
llvm-svn: 86404
2009-11-07 21:25:39 +00:00
3467dcb12d
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
...
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
llvm-svn: 86319
2009-11-07 00:54:36 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
5ac6f244fd
Fix schedule model for BFC.
...
llvm-svn: 85809
2009-11-02 17:28:36 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
...
opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
e4b80c9bee
Add an indirect branch pattern for ARM. Testcase will be coming soon.
...
llvm-svn: 85355
2009-10-28 00:37:03 +00:00
cde65ec581
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
...
llvm-svn: 85299
2009-10-27 20:51:49 +00:00
4f36affe5f
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
...
BL_pred and BLr9_pred.
llvm-svn: 85297
2009-10-27 20:45:15 +00:00
b5044ce5a9
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
...
instruction format that already takes care of setting this.
llvm-svn: 85280
2009-10-27 19:52:03 +00:00
df5dcdaa10
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
...
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
llvm-svn: 85271
2009-10-27 18:44:24 +00:00
13edef55b6
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85178
2009-10-26 23:45:59 +00:00
a33fa47141
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
...
bits. Johnny, please review -- I do not have a good track record of getting
these right.
llvm-svn: 85173
2009-10-26 22:59:12 +00:00
a6aba77e0a
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
...
bits. Patch by Johnny Chen.
llvm-svn: 85167
2009-10-26 22:34:44 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
2f69ed8f4c
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
...
llvm-svn: 84573
2009-10-20 00:40:56 +00:00
1a791eedbf
Set instruction encoding bits 4 and 7 for ARM register-register and
...
register-shifted-register instructions. Patch by Johnny Chen.
llvm-svn: 84124
2009-10-14 19:00:24 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
...
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
453a06e3ac
Add some ARM instruction encoding bits.
...
Patch by Johnny Chen.
llvm-svn: 83983
2009-10-13 17:35:30 +00:00
0bc673de0d
Fix a tab. Thanks to Johnny Chen for pointing it out.
...
llvm-svn: 83973
2009-10-13 15:27:23 +00:00
4a72f7ab53
Mark the LDR instruction with isReMaterializable, as it is rematerializable
...
when loading from an invariant memory location.
llvm-svn: 83688
2009-10-09 23:28:27 +00:00
dc7d1ce575
Fix a comment typo.
...
Patch by Johnny Chen.
llvm-svn: 83407
2009-10-06 20:18:46 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
...
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
...
Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
...
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
c30d816d7a
Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument.
...
Disable rematting of it for now.
llvm-svn: 82975
2009-09-28 07:26:46 +00:00
7c2b1e71c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
...
This should be better than single load from constpool.
llvm-svn: 82948
2009-09-27 23:52:58 +00:00
9fa8345b65
Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set.
...
llvm-svn: 81310
2009-09-09 01:47:07 +00:00
d93c668f00
Calls clobber FPSCR.
...
llvm-svn: 80956
2009-09-03 22:12:28 +00:00
5f582b7290
RRX reads CPSR.
...
llvm-svn: 80699
2009-09-01 18:32:09 +00:00
4047b53a40
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
...
llvm-svn: 80350
2009-08-28 06:59:37 +00:00
209baa5c48
STRD and LDRD require ARMv5TE, not just ARMv5T.
...
See http://llvm.org/PR4687 for more info and links.
llvm-svn: 80244
2009-08-27 14:14:21 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
...
llvm-svn: 79436
2009-08-19 18:00:44 +00:00
eba70d85cf
Add missing defs of R2 and D1.
...
llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
...
llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
...
llvm-svn: 78904
2009-08-13 15:11:43 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
693e36a3e8
SjLj based exception handling unwinding support. This patch is nasty, brutish
...
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
llvm-svn: 78625
2009-08-11 00:09:57 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
...
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
...
llvm-svn: 78321
2009-08-06 16:52:47 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
...
llvm-svn: 78081
2009-08-04 17:53:06 +00:00
175bd14967
Make sure Thumb2 uses the right call instructions.
...
llvm-svn: 77507
2009-07-29 21:26:42 +00:00
0d98d8b8b3
- Fix an obvious copy and paste error.
...
- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
c6d70ae063
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
...
llvm-svn: 77422
2009-07-29 02:18:14 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
...
llvm-svn: 77364
2009-07-28 20:53:24 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
...
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
...
llvm-svn: 76803
2009-07-22 22:03:29 +00:00
4b02b2f79c
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
...
llvm-svn: 76729
2009-07-22 06:46:53 +00:00
bd9ba429ca
1. In Thumb mode, select tBx instead of ARM variants.
...
2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
llvm-svn: 75585
2009-07-14 01:49:27 +00:00
72b80ac9b1
Fix detection of valid BFC immediates.
...
llvm-svn: 75576
2009-07-14 00:57:56 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
...
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
a02fc2d327
LDM_RET should be marked mayLoad.
...
llvm-svn: 75187
2009-07-09 22:57:41 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
...
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
f0080b734a
Also statically set bit 25 for BR_JT instructions.
...
llvm-svn: 74974
2009-07-07 23:45:10 +00:00
2cff076cfe
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.
...
llvm-svn: 74972
2009-07-07 23:40:25 +00:00
02a44edf12
Add BX and BXr9 encodings. Patch by Sean Callanan.
...
llvm-svn: 74938
2009-07-07 19:16:24 +00:00
40398233b7
Add bfc to armv6t2.
...
llvm-svn: 74868
2009-07-06 22:23:46 +00:00
e63b0e6f79
Added ARM::mls for armv6t2.
...
llvm-svn: 74866
2009-07-06 22:05:45 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
...
llvm-svn: 74692
2009-07-02 06:38:40 +00:00
979da0e590
80 col violation.
...
llvm-svn: 74683
2009-07-02 01:30:04 +00:00
deb35afd23
Add a new addressing mode for NEON load/store instructions.
...
llvm-svn: 74658
2009-07-01 23:16:05 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
...
llvm-svn: 74423
2009-06-29 15:33:01 +00:00
b23b50d54d
Implement Thumb2 ldr.
...
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
1eda63715f
Simplify predicate CarryDefIsUsed.
...
llvm-svn: 74277
2009-06-26 06:10:18 +00:00
5bf9011c2d
Mark a bunch of instructions commutable.
...
llvm-svn: 74237
2009-06-26 00:19:44 +00:00
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
...
llvm-svn: 74228
2009-06-25 23:34:10 +00:00
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
...
llvm-svn: 74200
2009-06-25 20:59:23 +00:00
4c048fe5ad
80 col violation.
...
llvm-svn: 74138
2009-06-24 23:14:45 +00:00
431cf567de
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
...
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
llvm-svn: 73965
2009-06-23 17:48:47 +00:00
6a42ec3e70
Minor reorg.
...
llvm-svn: 73948
2009-06-23 05:25:29 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
...
This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
e67b77028e
Add explicit types for shift count constants. This is in preparation for
...
another change that makes the types ambiguous (at least as far as tablegen
is concerned).
llvm-svn: 73909
2009-06-22 22:08:29 +00:00
4582530a2c
For Darwin on ARMv6 and newer, make register r9 available for use as a
...
caller-saved register.
llvm-svn: 73901
2009-06-22 21:01:46 +00:00
4e712de541
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
...
llvm-svn: 73747
2009-06-19 01:51:50 +00:00
02bb33c58d
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
409105fc95
Rename methods for the sake of consistency.
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llvm-svn: 73428
2009-06-15 21:46:20 +00:00
1283c6a066
Part 1.
...
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
2009-06-15 08:28:29 +00:00
d93b5b672f
Mark some pattern-less instructions as neverHasSideEffects.
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llvm-svn: 73252
2009-06-12 20:46:18 +00:00
b6f4538683
Add placeholder for thumb2 stuff
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llvm-svn: 72593
2009-05-29 23:41:08 +00:00
06928192ae
Update the names of the exception handling sjlj instrinsics to
...
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
llvm-svn: 71758
2009-05-14 00:46:35 +00:00
aeca45dd6f
Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is
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a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.
llvm-svn: 71610
2009-05-12 23:59:14 +00:00
64fdacc27f
A few more isAsCheapAsAMove.
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llvm-svn: 63852
2009-02-05 08:42:55 +00:00
69cc2cbbff
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
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llvm-svn: 60487
2008-12-03 18:15:48 +00:00
30f6f8fdad
Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings.
...
llvm-svn: 59314
2008-11-14 20:09:11 +00:00
2666f59322
Fix pre- and post-indexed load / store encoding bugs.
...
llvm-svn: 59230
2008-11-13 07:34:59 +00:00
af644b50b4
Consolidate formats; fix FCMPED etc. encodings.
...
llvm-svn: 59107
2008-11-12 07:18:38 +00:00
7095cd2af2
Jump table JIT support. Work in progress.
...
llvm-svn: 58836
2008-11-07 09:06:08 +00:00
98dc53e926
Encode misc arithmetic instructions.
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llvm-svn: 58828
2008-11-07 01:41:35 +00:00
49d665218c
Encode extend instructions; more clean up.
...
llvm-svn: 58818
2008-11-06 22:15:19 +00:00
aa03cd3336
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
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- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
47b546d75f
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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llvm-svn: 58800
2008-11-06 08:47:38 +00:00
36ae40342f
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
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llvm-svn: 58793
2008-11-06 03:35:07 +00:00
b870fd8874
Fix so_imm encoding bug; add support for MOVi2pieces.
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llvm-svn: 58790
2008-11-06 02:25:39 +00:00
2686c8fb34
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
...
llvm-svn: 58789
2008-11-06 01:21:28 +00:00
fd2adbfa28
Encode pic load / store instructions; fix some encoding bugs.
...
llvm-svn: 58780
2008-11-05 23:22:34 +00:00
81889d010c
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
...
llvm-svn: 58764
2008-11-05 18:35:52 +00:00
4d0549e3be
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
...
llvm-svn: 58626
2008-11-03 18:38:31 +00:00
8fce66a47c
Forgot this in last commit.
...
llvm-svn: 58527
2008-10-31 19:11:09 +00:00
b7c01f5f48
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
...
llvm-svn: 57524
2008-10-14 20:36:24 +00:00
2753955fc0
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
...
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
llvm-svn: 57385
2008-10-11 22:08:30 +00:00
f311fe142c
Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits.
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llvm-svn: 57262
2008-10-07 21:08:09 +00:00
1d54d4f375
Fix Opcode values of CMP and CMN
...
llvm-svn: 57251
2008-10-07 17:40:46 +00:00
7848cfcd77
Fix addrmode1 instruction encodings; fix bx_ret encoding.
...
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
12134701ec
Revert 56176. All those instruction formats are still needed.
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llvm-svn: 56180
2008-09-13 01:35:33 +00:00
c5c74f36fd
Eliminate unnecessary instruction formats.
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llvm-svn: 56176
2008-09-12 23:15:39 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
...
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
fa558788e7
Control flow instruction encodings.
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llvm-svn: 55601
2008-09-01 08:25:56 +00:00
c288cc0572
ldm / stm instruction encodings.
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llvm-svn: 55599
2008-09-01 07:48:18 +00:00
c37532b24a
AXI2 and AXI3 instruction encodings.
...
llvm-svn: 55598
2008-09-01 07:34:13 +00:00
169eccc24e
addrmode3 instruction encodings.
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llvm-svn: 55596
2008-09-01 07:00:14 +00:00
cccca875b1
Rest of addrmode2 instruction encodings.
...
llvm-svn: 55593
2008-09-01 01:27:33 +00:00
01fd3f129a
Addr2 word / byte load encodings.
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llvm-svn: 55591
2008-08-31 19:02:21 +00:00
9f717afd68
MVN is addrmode1.
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llvm-svn: 55530
2008-08-29 07:36:24 +00:00
2d37f19ef2
Refactor ARM instruction format definitions into a separate file. No functionality changes.
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llvm-svn: 55518
2008-08-28 23:39:26 +00:00
2ce6f2ad5e
Rename SDOperand to SDValue.
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llvm-svn: 54128
2008-07-27 21:46:04 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
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llvm-svn: 48380
2008-03-15 00:03:38 +00:00
97925ec704
Final de-tabification.
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llvm-svn: 47663
2008-02-27 06:33:05 +00:00
1ea55cf816
This commit changes:
...
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
2008-01-17 19:59:44 +00:00
9a249b0ce5
rename SDTRet -> SDTNone.
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Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
llvm-svn: 46017
2008-01-15 22:02:54 +00:00
94de7bc3aa
get def use info more correct.
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llvm-svn: 45821
2008-01-10 05:12:37 +00:00
7250120177
Only mark instructions that load a single value without extension as isSimpleLoad = 1.
...
llvm-svn: 45727
2008-01-07 23:56:57 +00:00
a4ce4f6987
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
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llvm-svn: 45667
2008-01-06 23:38:27 +00:00
10324d0175
rename isStore -> mayStore to more accurately reflect what it captures.
...
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
f4d55ec4e8
remove explicit isStore flags that are now inferrable.
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llvm-svn: 45653
2008-01-06 05:55:01 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
6e68381e02
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
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llvm-svn: 44960
2007-12-12 23:12:09 +00:00
77b13af9a6
Unifacalize the CALLSEQ{START,END} stuff.
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llvm-svn: 44045
2007-11-13 09:19:02 +00:00
f359fed9f9
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
...
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
933b5b7e62
Add a flag for indirect branch instructions.
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Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
f948772f9e
80 col.
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llvm-svn: 41812
2007-09-10 22:22:23 +00:00
73489273ae
ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
...
llvm-svn: 41626
2007-08-30 23:25:47 +00:00
f7c6effc44
Initial JIT support for ARM by Raul Fernandes Herbster.
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llvm-svn: 40887
2007-08-07 01:37:15 +00:00
aa39b39eec
Indexed loads each has 2 outputs.
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llvm-svn: 40658
2007-08-01 00:12:08 +00:00
ac1591be42
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
...
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
881248c4e1
No need for ccop anymore.
...
llvm-svn: 37965
2007-07-06 23:34:09 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
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llvm-svn: 37961
2007-07-06 23:22:46 +00:00
5c66888580
PredicateDefOperand -> OptionalDefOperand.
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llvm-svn: 37931
2007-07-06 01:00:49 +00:00
085314b455
Unbreak the build.
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llvm-svn: 37914
2007-07-05 17:13:19 +00:00
aa3b8014bd
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
...
llvm-svn: 37895
2007-07-05 07:13:32 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
0c550df9d2
Fix the build.
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llvm-svn: 37705
2007-06-22 16:59:54 +00:00
c3c949b473
Allow predicated immediate ARM to ARM calls.
...
llvm-svn: 37659
2007-06-19 21:05:09 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
...
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
e8c3cbf971
Mark these instructions clobbersPred. They modify the condition code register.
...
llvm-svn: 37468
2007-06-06 10:17:05 +00:00
9aa5fc8577
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
...
llvm-svn: 37388
2007-06-01 20:51:29 +00:00
a2ab4e5feb
Make jumptable non-predicable for now.
...
llvm-svn: 37381
2007-06-01 00:56:15 +00:00
a6e9a4ce07
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
...
llvm-svn: 37349
2007-05-29 23:32:06 +00:00
d1de276c16
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
...
llvm-svn: 37271
2007-05-21 22:42:04 +00:00
7d55f3733e
Add some patterns for PIC PC-relative loads and stores.
...
llvm-svn: 37269
2007-05-21 22:14:33 +00:00
4ae1840d21
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
...
llvm-svn: 37199
2007-05-18 01:53:54 +00:00
dcd6cdf896
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
...
llvm-svn: 37118
2007-05-16 20:50:01 +00:00
Johnny Chen