2de229f31b
Fix bug: test/Regression/Transforms/LowerInvoke/2004-02-29-PHICrash.llx
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... which tickled the lowerinvoke pass because it used the BCE routines.
llvm-svn: 12012
2004-02-29 22:24:41 +00:00
9c9a4c4abd
Testcase for a bug that caused a whole bunch of testcases to die in the nightly
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tester last night.
llvm-svn: 12011
2004-02-29 22:15:51 +00:00
604cc83933
Add an assert
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llvm-svn: 12010
2004-02-29 22:01:51 +00:00
e0c3c18802
Add back #include I messed up
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llvm-svn: 12009
2004-02-29 21:40:53 +00:00
90ecb92838
Urg, forgot to check this in.
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llvm-svn: 12007
2004-02-29 21:03:08 +00:00
f2bb31c5fd
Module does not need to be annotatable aka annotable
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llvm-svn: 12005
2004-02-29 19:27:55 +00:00
fcb4f9d00b
Remove public header. It's been moved to lib/Target/SparcV9
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llvm-svn: 12004
2004-02-29 19:13:20 +00:00
3859031b9b
Move the private MachineInstrAnnot.h into a private directory.
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llvm-svn: 12003
2004-02-29 19:12:51 +00:00
d5a49c477d
Remove use of an ugly header
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llvm-svn: 12002
2004-02-29 19:04:31 +00:00
6194ee84ba
Move methods out of .h file
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llvm-svn: 12001
2004-02-29 19:02:39 +00:00
23840c7db5
Do not use explicit casts that hide the dependence on Instruction being
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annotable
llvm-svn: 12000
2004-02-29 19:02:26 +00:00
79b8d467da
Ugh, the old sparc backend attaches MachineCodeForInstruction annotations on
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LLVM instructions. Because it contains an explicit cast, we didn't catch it.
I guess instruction's will be annotable for the duration of the sparcv9's
existence.
llvm-svn: 11999
2004-02-29 18:54:23 +00:00
9a4653edfa
Add instruction name description.
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llvm-svn: 11998
2004-02-29 18:44:03 +00:00
0824ffc697
Use correct template for SHLD and SHRD instructions so that the memory
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operand size is correctly specified.
llvm-svn: 11997
2004-02-29 09:19:40 +00:00
c7fd0770a0
Improve allocation order:
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1) For 8-bit registers try to use first the ones that are parts of the
same register (AL then AH). This way we only alias 2 16/32-bit
registers after allocating 4 8-bit variables.
2) Move EBX as the last register to allocate. This will cause less
spills to happen since we will have 8-bit registers available up to
register excaustion (assuming we use the allocation order). It
would be nice if we could push all of the 8-bit aliased registers
towards the end but we much prefer to keep callee saved register to
the end to avoid saving them on entry and exit of the function.
For example this gives a slight reduction of spills with linear scan
on 164.gzip.
Before:
11221 asm-printer - Number of machine instrs printed
975 spiller - Number of loads added
675 spiller - Number of stores added
398 spiller - Number of register spills
After:
11182 asm-printer - Number of machine instrs printed
952 spiller - Number of loads added
652 spiller - Number of stores added
386 spiller - Number of register spills
llvm-svn: 11996
2004-02-29 09:17:01 +00:00
ea81b79a97
A big X86 instruction rename. The instructions are renamed to make
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their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:
ADD8rr -> add, 8-bit register, 8-bit register
IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
llvm-svn: 11995
2004-02-29 08:50:03 +00:00
2f80d586b8
Remove dead member variables of SparcV9SchedInfo and TargetSchedInfo
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llvm-svn: 11994
2004-02-29 08:40:03 +00:00
1e36fb030c
Eliminate the X86-specific BMI functions, using BuildMI instead.
...
Replace uses of addZImm with addImm.
llvm-svn: 11992
2004-02-29 07:22:16 +00:00
9a97573267
Fix a miscompilation of 197.parser that occurs when you have single basic
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block loops.
llvm-svn: 11990
2004-02-29 07:10:16 +00:00
bf2963ef91
Fix PR255: [tailduplication] Single basic block loops are very rare
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Note that this is a band-aid put over a band-aid. This just undisables
tail duplication in on very specific case that it seems to work in.
llvm-svn: 11989
2004-02-29 06:41:20 +00:00
d470a0f042
Update comment at head of file. Also fix C 'typedef struct' nonsense I
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inadvertently left in here.
llvm-svn: 11988
2004-02-29 06:33:28 +00:00
ed01da8f0b
Adjust to change in TII ctor arguments
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llvm-svn: 11987
2004-02-29 06:31:44 +00:00
f20abac9bc
Eliminate the distinction between "real" and "unreal" instructions
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llvm-svn: 11986
2004-02-29 06:31:16 +00:00
e65125dcdf
Add more architectures, and ELF64 stuff.
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llvm-svn: 11985
2004-02-29 06:30:25 +00:00
ca89812db7
These two virtual methods are never called.
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llvm-svn: 11984
2004-02-29 05:59:33 +00:00
71a899dea6
Remove a TON of flags that noone cares about
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llvm-svn: 11983
2004-02-29 05:58:30 +00:00
59d9e9126d
Noone calls these virtual methods
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llvm-svn: 11982
2004-02-29 05:58:16 +00:00
79d9a93a71
This is the only file in the system that uses this enum. eliminate it.
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llvm-svn: 11981
2004-02-29 05:57:59 +00:00
f611ca055c
Scrap a huge layer of cruft out of this interface.
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llvm-svn: 11980
2004-02-29 05:57:21 +00:00
e5f08917ae
Implement initial prolog/epilog code insertion methods.
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llvm-svn: 11979
2004-02-29 05:18:30 +00:00
5e7b3180e5
Remove unneeded #include
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llvm-svn: 11978
2004-02-29 05:15:56 +00:00
44b1b22a2d
int64_t -> int
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llvm-svn: 11977
2004-02-29 05:07:02 +00:00
a33f2b3731
Continue Alkis's int64_t cleanup. This makes all of the immediate related
...
methods take an int or unsigned value instead of int64_t.
Also, add an 'addImm' method to the MachineInstrBuilder class, because the
fact that the hardware sign or zero extends it does not/should not matter
to the code generator. Once the old sparc backend is removed the difference
can be eliminated.
llvm-svn: 11976
2004-02-29 05:06:49 +00:00
349b8c928d
Add BuildMI variants that take a MBB::iterator
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llvm-svn: 11975
2004-02-29 04:55:28 +00:00
876f6f96d0
Use correct template for ADC instruction with memory operands.
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llvm-svn: 11974
2004-02-29 02:18:17 +00:00
b1862e4d3b
Add an instruction selector capable of selecting 'ret void'
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llvm-svn: 11973
2004-02-29 00:27:00 +00:00
fa63580517
SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them
...
to denote this fact.
llvm-svn: 11972
2004-02-28 23:46:44 +00:00
4953ae085a
Floating point loads/stores act on memory operands. Rename them to
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denote this fact.
llvm-svn: 11971
2004-02-28 23:42:35 +00:00
c6948fa762
Rename instruction templates to be easier to the human eye to
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parse. The name is now I (operand size)*. For example:
Im32 -> instruction with 32-bit memory operands.
Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
operands.
llvm-svn: 11970
2004-02-28 23:09:03 +00:00
5b5dee4afb
Uncomment instructions that take both an immediate and a memory
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operand but their sizes differ.
llvm-svn: 11969
2004-02-28 22:06:59 +00:00
c0f3741a16
Fix my sloppiness
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llvm-svn: 11968
2004-02-28 22:06:03 +00:00
194939086d
Each instruction now has both an ImmType and a MemType. This describes
...
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).
llvm-svn: 11967
2004-02-28 22:02:05 +00:00
465a5cc291
Fix typo in comment
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llvm-svn: 11966
2004-02-28 21:55:18 +00:00
c116ede471
Add a testcase for switch instruction induction
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llvm-svn: 11965
2004-02-28 21:30:39 +00:00
d3e6ae263c
Implement switch->br and br->switch folding by ripping out the switch->switch
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and br->br code and generalizing it. This allows us to compile code like this:
int test(Instruction *I) {
if (isa<CastInst>(I))
return foo(7);
else if (isa<BranchInst>(I))
return foo(123);
else if (isa<UnwindInst>(I))
return foo(1241);
else if (isa<SetCondInst>(I))
return foo(1);
else if (isa<VAArgInst>(I))
return foo(42);
return foo(-1);
}
into:
int %_Z4testPN4llvm11InstructionE("struct.llvm::Instruction"* %I) {
entry:
%tmp.1.i.i.i.i.i.i.i = getelementptr "struct.llvm::Instruction"* %I, long 0, ubyte 4 ; <uint*> [#uses=1]
%tmp.2.i.i.i.i.i.i.i = load uint* %tmp.1.i.i.i.i.i.i.i ; <uint> [#uses=2]
%tmp.2.i.i.i.i.i.i = seteq uint %tmp.2.i.i.i.i.i.i.i, 27 ; <bool> [#uses=0]
switch uint %tmp.2.i.i.i.i.i.i.i, label %endif.0 [
uint 27, label %then.0
uint 2, label %then.1
uint 5, label %then.2
uint 14, label %then.3
uint 15, label %then.3
uint 16, label %then.3
uint 17, label %then.3
uint 18, label %then.3
uint 19, label %then.3
uint 32, label %then.4
]
...
As well as handling the cases in 176.gcc and many other programs more effectively.
llvm-svn: 11964
2004-02-28 21:28:10 +00:00
72bb8fcb15
Change this so that LLC actually tries to run the code generator, though it will
...
immediately abort due to lack of an instruction selector. :)
llvm-svn: 11963
2004-02-28 20:21:45 +00:00
72170c4a2e
Add a hook to run with the V8 target, though it doesn't currently work. Also
...
mark the PPC backend as experimental
llvm-svn: 11962
2004-02-28 19:55:16 +00:00
fc5232ba3a
Add hook for V8 target
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llvm-svn: 11961
2004-02-28 19:54:16 +00:00
990c279f5c
SparcV8 now builds.
...
llvm-svn: 11960
2004-02-28 19:54:00 +00:00
daeeaa72cd
fine grainify namespacification
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llvm-svn: 11959
2004-02-28 19:53:18 +00:00
Chris Lattner