Commit Graph

1853 Commits

Author SHA1 Message Date
Chris Lattner 87bb642676 @GOTPCREL is also rip-relative. Fix fast-isel to do the right thing.
This fixes an llvm-gcc bootstrap problem I introduced.

llvm-svn: 74691
2009-07-02 04:22:01 +00:00
Chris Lattner d1c5951615 Fix yet-another bug I introduced into fastisel, this time handling
constant pool references that weren't getting properly rip-relative.

llvm-svn: 74689
2009-07-02 03:14:25 +00:00
Chris Lattner 1f50b61329 Fix codegen for references to available_externally symbols. This fixes
PR4482.

llvm-svn: 74613
2009-07-01 16:53:44 +00:00
Evan Cheng 04f72fc955 CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).
llvm-svn: 74602
2009-07-01 08:29:08 +00:00
Evan Cheng 2a5efe14a7 Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.

llvm-svn: 74601
2009-07-01 08:19:36 +00:00
Chris Lattner f95fa1b721 Fix some fast-isel problems selecting global variable addressing in
pic mode.

llvm-svn: 74582
2009-07-01 03:27:19 +00:00
Evan Cheng d379e896ff Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
llvm-svn: 74580
2009-07-01 01:59:31 +00:00
David Goodwin 86c7e20ca6 Add PIC load and store patterns for Thumb-2.
llvm-svn: 74577
2009-07-01 00:01:13 +00:00
David Goodwin d0890a2bad Add thumb-2 store word, halfword, and byte.
llvm-svn: 74555
2009-06-30 22:11:34 +00:00
David Goodwin 28d6d87244 Improve Thumb-2 jump table support.
llvm-svn: 74549
2009-06-30 19:50:22 +00:00
Rafael Espindola 317fd045e2 Fix PR4485.
Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.

llvm-svn: 74534
2009-06-30 16:40:03 +00:00
Rafael Espindola bd971ffcc6 Fix PR4484.
This was caused by me confounding FP0 and ST(0).

llvm-svn: 74523
2009-06-30 12:18:16 +00:00
Evan Cheng dcf1f59305 Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).
llvm-svn: 74519
2009-06-30 09:19:42 +00:00
Evan Cheng 0dc101b897 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
2009-06-30 08:49:04 +00:00
Evan Cheng 57726817aa A few more load instructions.
llvm-svn: 74500
2009-06-30 02:15:48 +00:00
David Goodwin 17512663f5 Enhance tests to include shifted-register operand testing.
llvm-svn: 74490
2009-06-30 01:02:20 +00:00
David Goodwin 76b37950ca Add Thumb-2 support for TEQ amd TST.
llvm-svn: 74468
2009-06-29 22:49:42 +00:00
David Goodwin 911edef65b Thumb-2 tests
llvm-svn: 74464
2009-06-29 22:25:22 +00:00
Rafael Espindola 538064d6b1 FIX PR 4459.
Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.

llvm-svn: 74446
2009-06-29 20:29:59 +00:00
David Goodwin dbf11ba800 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
llvm-svn: 74423
2009-06-29 15:33:01 +00:00
Evan Cheng b23b50d54d Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
2009-06-29 07:51:04 +00:00
Chris Lattner 9876bd8257 factor some logic out into a helper function, allow remat of loads from constant
globals.  This implements remat-constant.ll even without aggressive-remat.

llvm-svn: 74373
2009-06-27 04:38:55 +00:00
Chris Lattner fea81da433 Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not.  Instead, those decisions are made by isel lowering
and propagated through to the asm printer.  To achieve this, we:

1. Represent RIP relative addresses by setting the base of the X86 addr
   mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
   X86ISD::WrapperRIP.  When it is unsafe to use RIP, it lowers to
   X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
   a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
   passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
   when to emit (%rip), they just print the symbol.

I think this is a big improvement over the previous situation.  It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier.  This is a short term hack, there is
a much better, but more involved, solution.  2. I had to xfail an 
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction.  This specific test is easy to fix without
-aggressive-remat, which I intend to do next.

llvm-svn: 74372
2009-06-27 04:16:01 +00:00
Chris Lattner df92e147c9 remove some unneeded eh info.
llvm-svn: 74371
2009-06-27 04:07:31 +00:00
Chris Lattner de36afc1fe testcase for PR4466
llvm-svn: 74367
2009-06-27 01:33:35 +00:00
David Goodwin 5285817490 When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
llvm-svn: 74355
2009-06-26 23:13:13 +00:00
Dan Gohman d3b930d426 Add some testcases for some of the recent ScalarEvolution bug fixes.
llvm-svn: 74353
2009-06-26 22:54:11 +00:00
David Goodwin 3aaa751712 Thumb-2 tests
llvm-svn: 74345
2009-06-26 22:37:07 +00:00
Chris Lattner b5c2639f83 remove unwind info, add test for asmprinting of jump table labels with (%rip)
llvm-svn: 74337
2009-06-26 22:16:49 +00:00
Evan Cheng 07b016856d Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work.
llvm-svn: 74336
2009-06-26 22:00:19 +00:00
David Goodwin aa294c5593 Thumb-2 has CLZ.
llvm-svn: 74322
2009-06-26 20:47:43 +00:00
David Goodwin 35ee722d42 Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
llvm-svn: 74321
2009-06-26 20:45:56 +00:00
Daniel Dunbar a720af1370 More spelling Count as count.
llvm-svn: 74306
2009-06-26 18:35:07 +00:00
Daniel Dunbar 6b1678d5d8 Spell Count as count.
llvm-svn: 74298
2009-06-26 18:21:54 +00:00
David Goodwin 3bd42afebe Add Thumb-2 tests.
llvm-svn: 74295
2009-06-26 18:10:30 +00:00
David Goodwin 5960e6d974 ADC used to implement adde should use "adcs" opcode instead of "adc".
llvm-svn: 74293
2009-06-26 18:07:25 +00:00
David Goodwin 34f7ede9e7 ORN and BIC tests.
llvm-svn: 74289
2009-06-26 16:20:06 +00:00
David Goodwin 0377f737ff Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288
2009-06-26 16:10:07 +00:00
Evan Cheng 7779156b39 Fix tests: Count -> count.
llvm-svn: 74282
2009-06-26 07:05:57 +00:00
Evan Cheng 34c8c7414f Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
llvm-svn: 74276
2009-06-26 05:59:16 +00:00
Daniel Dunbar 07025e2c02 Fix spelling of 'count'
llvm-svn: 74249
2009-06-26 01:33:02 +00:00
Evan Cheng 97727a61f9 Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
llvm-svn: 74228
2009-06-25 23:34:10 +00:00
David Goodwin 16f357cccf Use MVN for ~t2_so_imm immediates.
llvm-svn: 74223
2009-06-25 23:11:21 +00:00
Bill Wendling 722c6e1b70 Don't grep the -debug output. This isn't the way to test changes.
llvm-svn: 74211
2009-06-25 21:59:32 +00:00
Chris Lattner a4194b1082 down with unwind info :)
llvm-svn: 74206
2009-06-25 21:48:17 +00:00
Evan Cheng c7ea8df67e ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
llvm-svn: 74200
2009-06-25 20:59:23 +00:00
Evan Cheng 83f979a48b Add Thumb2 pc relative add.
llvm-svn: 74141
2009-06-24 23:47:58 +00:00
Evan Cheng ff1a4a7271 We should run these tests as well.
llvm-svn: 74121
2009-06-24 21:36:26 +00:00
Chris Lattner 01d5049dc2 unwind info not needed.
llvm-svn: 74112
2009-06-24 19:48:04 +00:00
Evan Cheng d76d0aa68a Move thumb and thumb2 tests into separate directories.
llvm-svn: 74068
2009-06-24 06:36:07 +00:00