844f0b4562
80 col violation.
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llvm-svn: 74693
2009-07-02 06:44:30 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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llvm-svn: 74692
2009-07-02 06:38:40 +00:00
87bb642676
@GOTPCREL is also rip-relative. Fix fast-isel to do the right thing.
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This fixes an llvm-gcc bootstrap problem I introduced.
llvm-svn: 74691
2009-07-02 04:22:01 +00:00
d1c5951615
Fix yet-another bug I introduced into fastisel, this time handling
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constant pool references that weren't getting properly rip-relative.
llvm-svn: 74689
2009-07-02 03:14:25 +00:00
eefbf1961c
Remove getFunctionAlignment from TargetELFInfo and use new MachineFunction alignment method
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llvm-svn: 74686
2009-07-02 02:13:13 +00:00
979da0e590
80 col violation.
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llvm-svn: 74683
2009-07-02 01:30:04 +00:00
4ec83ea628
clarify: stub emission depends on the version of the linker you use, it has nothing
...
to do with the target. Also, the stub elimination optimization *requires* making the
stub explicit.
llvm-svn: 74682
2009-07-02 01:24:34 +00:00
d9c55368e7
Factor out ARM indexed load matching code.
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llvm-svn: 74681
2009-07-02 01:23:32 +00:00
43f33dd550
Fix a bunch of other places that used operator[] to test whether
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a key is present in a std::map or DenseMap to use find instead.
llvm-svn: 74676
2009-07-02 00:17:47 +00:00
4e6044c405
Add darwin stub removal to wishlist.
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llvm-svn: 74667
2009-07-01 23:36:02 +00:00
deb35afd23
Add a new addressing mode for NEON load/store instructions.
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llvm-svn: 74658
2009-07-01 23:16:05 +00:00
affb68bd08
Fix a comment typo.
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llvm-svn: 74650
2009-07-01 21:59:43 +00:00
bbbf805049
Fix up a comment: besides the >80col lines, the operation for this
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addressing mode is encoded in the second operand, not the third.
llvm-svn: 74641
2009-07-01 21:22:45 +00:00
512ff7353e
Update comments to make it clear that the function alignment is the Log2 of the
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bytes and not bytes.
llvm-svn: 74624
2009-07-01 18:50:55 +00:00
1f50b61329
Fix codegen for references to available_externally symbols. This fixes
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PR4482.
llvm-svn: 74613
2009-07-01 16:53:44 +00:00
f95fa1b721
Fix some fast-isel problems selecting global variable addressing in
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pic mode.
llvm-svn: 74582
2009-07-01 03:27:19 +00:00
d379e896ff
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
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llvm-svn: 74580
2009-07-01 01:59:31 +00:00
75c12e1569
Remove unused AsmPrinter OptLevel argument, and propogate.
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- This more or less amounts to a revert of r65379. I'm curious to know what
happened that caused this variable to become unused.
llvm-svn: 74579
2009-07-01 01:48:54 +00:00
86c7e20ca6
Add PIC load and store patterns for Thumb-2.
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llvm-svn: 74577
2009-07-01 00:01:13 +00:00
a83100f687
Thumb-2 load and store double description. But nothing yet creates them.
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llvm-svn: 74566
2009-06-30 22:50:01 +00:00
31ceb1bcba
Add an "alignment" field to the MachineFunction object. It makes more sense to
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have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
llvm-svn: 74564
2009-06-30 22:38:32 +00:00
d0890a2bad
Add thumb-2 store word, halfword, and byte.
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llvm-svn: 74555
2009-06-30 22:11:34 +00:00
28d6d87244
Improve Thumb-2 jump table support.
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llvm-svn: 74549
2009-06-30 19:50:22 +00:00
50475de6af
Add 256-bit memory operand support.
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llvm-svn: 74548
2009-06-30 19:24:59 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
317fd045e2
Fix PR4485.
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Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.
llvm-svn: 74534
2009-06-30 16:40:03 +00:00
bd971ffcc6
Fix PR4484.
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This was caused by me confounding FP0 and ST(0).
llvm-svn: 74523
2009-06-30 12:18:16 +00:00
0dc101b897
Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
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The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.
This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.
llvm-svn: 74518
2009-06-30 08:49:04 +00:00
b127c0684f
remove a bogus note.
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llvm-svn: 74509
2009-06-30 05:22:31 +00:00
5ed255e642
add a note
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llvm-svn: 74508
2009-06-30 04:20:46 +00:00
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
8adf1fdc80
Add a 256-bit register class and YMM registers.
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llvm-svn: 74469
2009-06-29 22:50:51 +00:00
76b37950ca
Add Thumb-2 support for TEQ amd TST.
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llvm-svn: 74468
2009-06-29 22:49:42 +00:00
538064d6b1
FIX PR 4459.
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Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.
llvm-svn: 74446
2009-06-29 20:29:59 +00:00
45c299ef65
Add a target-specific DAG combine on X86 to fold the common pattern of
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fence-atomic-fence down to just the atomic op. This is possible thanks to
X86's relatively strong memory model, which guarantees that locked instructions
(which are used to implement atomics) are implicit fences.
llvm-svn: 74435
2009-06-29 18:04:45 +00:00
46b56ffae3
Add processor descriptions for Istanbul and Shanghai.
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llvm-svn: 74429
2009-06-29 16:54:06 +00:00
a4b8998fbb
Fix a subtarget feature bug.
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llvm-svn: 74428
2009-06-29 16:51:01 +00:00
f92ba97cda
Add more vector ValueTypes for AVX and other extended vector instruction
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sets.
llvm-svn: 74427
2009-06-29 16:47:10 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
24a3724b04
Include the new file ThumbRegisterInfo.cpp to CMakeLists.txt
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to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.
llvm-svn: 74421
2009-06-29 13:11:32 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
0f2158b35f
Simplify a bit
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llvm-svn: 74385
2009-06-27 12:59:03 +00:00
a1b5b18bd0
ARM refactoring. Step 2: split RegisterInfo
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llvm-svn: 74384
2009-06-27 12:16:40 +00:00
33400e3670
Add ThumbInstrInfo.cpp to the CMake makefiles
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llvm-svn: 74382
2009-06-27 07:44:59 +00:00
1ec3afdc66
remove a bunch of fixmes (old checking code) and commonize all the
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target-specific operand printing functionality. Yay.
llvm-svn: 74379
2009-06-27 05:46:24 +00:00
ae0acfcef0
pull @GOT, @GOTOFF, @GOTPCREL handling into isel from the asmprinter.
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llvm-svn: 74378
2009-06-27 05:39:56 +00:00
cce1589e4e
simplify some code and eliminate the symbolicAddressesAreRIPRel() predicate.
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llvm-svn: 74377
2009-06-27 05:24:12 +00:00
d17366ae72
fix clang/test/CodeGenObjC/try.m, a basereg doesn't mean no global anymore.
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llvm-svn: 74375
2009-06-27 04:50:14 +00:00
014e83d40d
fix a bunch of failures in the X86-64 JIT by tolerating RIP as
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a base register. We just ignore it for now.
llvm-svn: 74374
2009-06-27 04:46:33 +00:00
9876bd8257
factor some logic out into a helper function, allow remat of loads from constant
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globals. This implements remat-constant.ll even without aggressive-remat.
llvm-svn: 74373
2009-06-27 04:38:55 +00:00
Evan Cheng