2edb4b7f99
Add empty patterns to all F3_1 instructions
...
llvm-svn: 24776
2005-12-17 18:49:14 +00:00
1d71248392
Darwin API issue: indirect load of external and weak symbols.
...
llvm-svn: 24775
2005-12-17 09:13:43 +00:00
866cef563b
Add some simple integer patterns. This allows us to compile this:
...
int %test(int %A) {
%B = add int %A, 1
%C = xor int %B, 123
ret int %C
}
into this:
test:
save -96, %sp, %sp
add %i0, 1, %l0
xor %l0, 123, %i0
restore %g0, %g0, %g0
retl
nop
for example. I guess it would make sense to add reg/reg versions too.
llvm-svn: 24774
2005-12-17 08:26:38 +00:00
80a3875bc1
Implement ret with operand, giving us this:
...
int %test(int %A) {
ret int %A
}
llvm-svn: 24773
2005-12-17 08:15:09 +00:00
1136b7a2e0
Add a pattern for 'ret'. This now compiles:
...
void %test() { ret void }
:)
llvm-svn: 24772
2005-12-17 08:08:42 +00:00
1549e4d590
Add empty patterns for F3_2 instructions
...
llvm-svn: 24771
2005-12-17 08:06:43 +00:00
9f1c860e1e
Implement LowerArguments, at least for the first 6 integer args
...
llvm-svn: 24770
2005-12-17 08:03:24 +00:00
4f34e9f7ff
Add the framework for a dag-dag isel
...
llvm-svn: 24769
2005-12-17 07:47:01 +00:00
f3b16bc5a0
Remove a few lines of dead code.
...
llvm-svn: 24768
2005-12-17 07:18:44 +00:00
69b5d17f92
asmprinter done, added crucial missing step
...
llvm-svn: 24767
2005-12-17 07:17:59 +00:00
55f9dbe1ea
Use the AsmPrinter for global variable init printing. This eliminates a
...
bunch of code and causes V8 to start using the fancy .asciz directive that
the sun assembler supports.
llvm-svn: 24766
2005-12-17 07:17:08 +00:00
fb7fd98cd4
Switch constant pool printing over to use the Shared AsmPrinter version
...
llvm-svn: 24765
2005-12-17 07:11:43 +00:00
b808c8e2e4
Use the shared AsmPrinter code for some basic stuff. No functionality
...
change except for fewer .section directives emitted
llvm-svn: 24764
2005-12-17 07:04:29 +00:00
7087cd275b
Added an idea about any_extend for performance tuning.
...
llvm-svn: 24763
2005-12-17 06:54:43 +00:00
9e2af046e4
Convert the remaining instructions over, branches and calls. Fix a couple
...
minor bugs
llvm-svn: 24762
2005-12-17 06:54:41 +00:00
6b669e2680
convert FP instructions to use an asmstring and operand list, allowing FP
...
programs to work on V8 again
llvm-svn: 24761
2005-12-17 06:32:52 +00:00
bc7708c0e8
Added truncate.
...
llvm-svn: 24760
2005-12-17 02:02:50 +00:00
b06925d1dd
Added anyext, modelled as zext on X86.
...
llvm-svn: 24759
2005-12-17 01:47:57 +00:00
e58ab48ccb
Yet another variant of getTargetNode().
...
llvm-svn: 24758
2005-12-17 01:44:51 +00:00
6b76009393
Added some isel ideas.
...
llvm-svn: 24757
2005-12-17 01:25:19 +00:00
cb19390ead
Added support for cmp, test, and conditional move instructions.
...
llvm-svn: 24756
2005-12-17 01:24:02 +00:00
0f68322992
Only lower SELECT when using DAG based isel.
...
llvm-svn: 24755
2005-12-17 01:22:13 +00:00
225a4d0d6d
X86 lowers SELECT to a cmp / test followed by a conditional move.
...
llvm-svn: 24754
2005-12-17 01:21:05 +00:00
e22f9181f7
Support for read / write from explicit registers with FlagVT type.
...
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
59dc6c553d
Fix VC++ level 4 warnings. Because a base class has declared these private, VC++ complains it cannot automatically generate this methods.
...
llvm-svn: 24751
2005-12-17 00:19:22 +00:00
ea36abe567
Fix VC++ level 4 warnings.
...
llvm-svn: 24750
2005-12-17 00:18:06 +00:00
9504149c1b
Turn on string pooling for smaller binaries.
...
llvm-svn: 24749
2005-12-17 00:14:47 +00:00
7c462768ed
Added source file/line correspondence for dwarf (PowerPC only at this point.)
...
llvm-svn: 24748
2005-12-16 22:45:29 +00:00
887af88ce3
Weak and linkonce global vars should still have a .globl emitted for them
...
llvm-svn: 24747
2005-12-16 21:46:14 +00:00
672578bd94
Add a second vector type to the VRRC register class, and fix some patterns
...
so that tablegen can infer all types.
llvm-svn: 24746
2005-12-16 09:19:13 +00:00
9f2c3a7c4e
add some notes
...
llvm-svn: 24745
2005-12-16 07:20:53 +00:00
fa55745cbc
Add a couple more instrs
...
llvm-svn: 24744
2005-12-16 07:18:48 +00:00
e082426ae7
remove some dead code
...
llvm-svn: 24743
2005-12-16 07:16:02 +00:00
70310906e7
asmprint pseudo instrs
...
llvm-svn: 24742
2005-12-16 07:13:26 +00:00
68d064a3a6
Autogenerate asmprinter for F3_2 instructions
...
llvm-svn: 24741
2005-12-16 07:10:02 +00:00
1e777082a0
Switch F3_1 instructions over to use AsmStrings
...
llvm-svn: 24740
2005-12-16 06:52:00 +00:00
4870224a56
Plug in basic hooks for an autogenerated asm printer to fill in.
...
llvm-svn: 24739
2005-12-16 06:34:17 +00:00
34e80f0114
Add operand info for F3_[12] instructions, getting V8 back to basic functionality.
...
With this, Regression/CodeGen/SparcV8/basictest.ll now passes. Lets hear it
for regression tests :)
llvm-svn: 24738
2005-12-16 06:25:42 +00:00
0d129ae8b1
A truly trivial testcase to ensure sparcv8 doesn't get completely broken
...
again.
llvm-svn: 24737
2005-12-16 06:24:55 +00:00
b527f48acd
Remove JIT support, which doesn't work.
...
llvm-svn: 24736
2005-12-16 06:06:07 +00:00
1e1ca1e9a5
add some simple operand info
...
llvm-svn: 24735
2005-12-16 06:02:58 +00:00
08a04cb3f2
rename option for consistency with -mcpu -mattr etc
...
llvm-svn: 24734
2005-12-16 05:19:55 +00:00
77e28af47d
rename options
...
llvm-svn: 24733
2005-12-16 05:19:35 +00:00
78e9e10b53
rename option
...
llvm-svn: 24732
2005-12-16 05:19:18 +00:00
3bf72b5c19
Document -mcpu -mattr -triple
...
llvm-svn: 24731
2005-12-16 05:18:53 +00:00
76766cb880
provide an option to override the target triple in a module from the commandline.
...
llvm-svn: 24730
2005-12-16 05:00:21 +00:00
e568b88c98
provide an option to override the target triple in a module from the command
...
line.
llvm-svn: 24729
2005-12-16 04:59:57 +00:00
575751151c
Update the darwin handling of linkonce & weak functions and GV stubs. This
...
should work in all permutations.
llvm-svn: 24728
2005-12-16 00:22:14 +00:00
9f62a2a51d
Don't globalize internal functions
...
llvm-svn: 24727
2005-12-16 00:07:30 +00:00
74151ba279
* Promote all 1 bit entities to 8 bit.
...
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
llvm-svn: 24726
2005-12-15 19:49:23 +00:00
83e4407379
Don't create SEXTLOAD/ZEXTLOAD instructions that the target doesn't support
...
if after legalize. This fixes IA64 failures.
llvm-svn: 24725
2005-12-15 19:02:38 +00:00
305c6a73b5
Added frameindex, constpool, globaladdr, and externalsym as root nodes of
...
leaaddr.
llvm-svn: 24724
2005-12-15 08:31:04 +00:00
a2ebc62862
Added constpool, frameindex, and externalsym nodes.
...
llvm-svn: 24723
2005-12-15 08:29:48 +00:00
00fcb0017e
Handling zero extension of 1 bit value.
...
llvm-svn: 24722
2005-12-15 01:02:48 +00:00
bc9344477e
Use MOV8rm to load 1 bit value.
...
llvm-svn: 24721
2005-12-15 00:59:17 +00:00
808f7a8abb
Remove a now unused statistic.
...
llvm-svn: 24720
2005-12-14 22:56:16 +00:00
e37cb604c1
Use the new predicate support that Evan Cheng added to remove some code
...
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
llvm-svn: 24719
2005-12-14 22:54:33 +00:00
7853983b40
Add a case for float just to make sure the patterns for both precisions
...
are matching
llvm-svn: 24718
2005-12-14 22:51:13 +00:00
023aef2f31
Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure.
...
llvm-svn: 24717
2005-12-14 22:28:18 +00:00
3db275d996
Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.
...
llvm-svn: 24716
2005-12-14 22:07:12 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
8dea0eca2f
Fix printing of the instructions.
...
llvm-svn: 24714
2005-12-14 22:01:07 +00:00
b8be9d1596
Fixed extload type profile. The 4th operand is a ValueType node with type
...
OtherVT, it cannot be compare to type of 1st operand which is an integer type.
llvm-svn: 24713
2005-12-14 19:40:54 +00:00
d39c60fcc8
When folding loads into ops, immediately replace uses of the op with the
...
load. This reduces number of worklist iterations and avoid missing optimizations
depending on folding of things into sext_inreg nodes (which aren't supported by
all targets).
Tested by Regression/CodeGen/X86/extend.ll:test2
llvm-svn: 24712
2005-12-14 19:25:30 +00:00
eaee560c96
new testcase, each function should have one extension instr in it
...
llvm-svn: 24711
2005-12-14 19:24:08 +00:00
4c10e7643f
Remove -start-group and -end-group no-op options, accidentally committed
...
in last patch.
llvm-svn: 24710
2005-12-14 19:08:51 +00:00
7dac1083da
Fix the (zext (zextload)) case to trigger, similarly for sign extends.
...
Allow (zext (truncate)) to apply after legalize if the target supports
AND (which all do).
This compiles
short %foo() {
%tmp.0 = load ubyte* %X ; <ubyte> [#uses=1]
%tmp.3 = cast ubyte %tmp.0 to short ; <short> [#uses=1]
ret short %tmp.3
}
to:
_foo:
movzbl _X, %eax
ret
instead of:
_foo:
movzbl _X, %eax
movzbl %al, %eax
ret
thanks to Evan for pointing this out.
llvm-svn: 24709
2005-12-14 19:05:06 +00:00
8c9e14620f
Fix Transforms/ScalarRepl/2005-12-14-UnionPromoteCrash.ll, a crash on undefined
...
behavior in 126.gcc on big-endian systems.
llvm-svn: 24708
2005-12-14 17:23:59 +00:00
f69abd13d4
new (undefined) testcase, distilled from 126.gcc that scalarrepl crashes on
...
llvm-svn: 24707
2005-12-14 17:23:20 +00:00
f753d1a574
Fix a miscompilation in crafty due to a recent patch
...
llvm-svn: 24706
2005-12-14 07:58:38 +00:00
c273900dd8
Added sext and zext patterns.
...
llvm-svn: 24705
2005-12-14 02:22:27 +00:00
6a31777c8e
Skip over srcvalue nodes when generating ISEL code.
...
llvm-svn: 24704
2005-12-14 02:21:57 +00:00
683d8515b1
Added sextld + zextld DAG nodes.
...
llvm-svn: 24703
2005-12-14 02:21:01 +00:00
bce7c47306
Fold (zext (load x) to (zextload x).
...
llvm-svn: 24702
2005-12-14 02:19:23 +00:00
40f081d8e0
Add support for fmul node of type v4f32.
...
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 00:34:09 +00:00
69caef2b78
Prepare support for AltiVec multiply, divide, and sqrt.
...
llvm-svn: 24700
2005-12-13 22:55:22 +00:00
6796b48e51
Adjust the constructor to the Linker class to take an argument that names
...
the module being constructed. This is used to correctly name the module.
Previously the name of the linker tool was used which produces confusing
output when the module identifier is used in an error message.
llvm-svn: 24699
2005-12-13 20:00:37 +00:00
175613adf6
Improve ResolveFunctions to:
...
a) use better local variable names (OldMT -> OldFT) where "M" is used to
mean "Function" (perhaps it was previously "Method"?)
b) print out the module identifier in a warning message so that it is
possible to track down in which module the error occurred.
llvm-svn: 24698
2005-12-13 19:56:51 +00:00
5d4e61dd87
Don't lump the filename and working dir together
...
llvm-svn: 24697
2005-12-13 17:40:33 +00:00
229f0ee6d7
Add load + store folding srl and sra patterns.
...
llvm-svn: 24696
2005-12-13 07:24:22 +00:00
87079884d1
Use the shared asmprinter code for printing special llvm globals
...
llvm-svn: 24695
2005-12-13 06:32:50 +00:00
f0e9aef954
Add a couple more fields, move ctor init list to .cpp file, add support
...
for emitting the ctor/dtor list for common targets.
llvm-svn: 24694
2005-12-13 06:32:10 +00:00
4d80f6e52e
Add ELF and darwin support for static ctors and dtors
...
llvm-svn: 24693
2005-12-13 04:53:51 +00:00
54a11df95d
reindent a loop, unswitch a loop. No functionality changes
...
llvm-svn: 24692
2005-12-13 04:33:58 +00:00
956aef45c9
Lowering constant pool entries on ppc exposed a bug in the recently added
...
ConstantVec legalizing code, which would return constantpool nodes that
were not of the target's pointer type.
llvm-svn: 24691
2005-12-13 03:03:23 +00:00
acec857b1a
Beautify a few patterns.
...
llvm-svn: 24690
2005-12-13 02:40:18 +00:00
89c6db4baf
Some shl patterns which do load + store folding.
...
llvm-svn: 24689
2005-12-13 02:34:51 +00:00
108beceb0f
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.
...
llvm-svn: 24688
2005-12-13 01:57:51 +00:00
ddd5ae5a22
Add and, or, and xor patterns which fold load + stores.
...
llvm-svn: 24687
2005-12-13 01:41:36 +00:00
e5a94a03e2
Add inc + dec patterns which fold load + stores.
...
llvm-svn: 24686
2005-12-13 01:02:47 +00:00
bde9e6fca6
Add neg and not patterns which fold load + stores.
...
llvm-svn: 24685
2005-12-13 00:54:44 +00:00
c414d563f0
Missed a couple redundant explicit type casts.
...
llvm-svn: 24684
2005-12-13 00:25:07 +00:00
62e6808aa5
Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.
...
llvm-svn: 24683
2005-12-13 00:14:11 +00:00
86b2cf22d2
* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
...
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.
llvm-svn: 24682
2005-12-13 00:01:09 +00:00
3e52756928
Add some integer mul patterns.
...
llvm-svn: 24681
2005-12-12 23:47:46 +00:00
6148153230
Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ...
...
llvm-svn: 24680
2005-12-12 23:45:21 +00:00
7e4c01eee3
At top of generated isel SelectCode() is this:
...
if (!N.Val->hasOneUse()) {
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
if (CGMI != CodeGenMap.end()) return CGMI->second;
}
Suppose a DAG like this:
X
^ ^
/ \
USE1 USE2
Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!
The fix is to always query CodeGenMap.
llvm-svn: 24679
2005-12-12 23:22:48 +00:00
9e8b633ec1
Accept and ignore prefetches for now
...
llvm-svn: 24678
2005-12-12 22:51:16 +00:00
b42ce7ca63
Fix CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
...
llvm-svn: 24677
2005-12-12 22:27:43 +00:00
1b668bc808
Testcase for a problem that reid ran into
...
llvm-svn: 24676
2005-12-12 22:27:22 +00:00
af3fe8217a
Add some sub patterns.
...
llvm-svn: 24675
2005-12-12 21:54:05 +00:00
67ed58e22b
When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
...
base or index operands being selected.
llvm-svn: 24674
2005-12-12 21:49:40 +00:00
bfd259a2b7
For ISD::RET, if # of operands >= 2, try selection the real data dep. operand
...
first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
llvm-svn: 24673
2005-12-12 20:32:18 +00:00
cd54254af3
fix FP selects
...
llvm-svn: 24672
2005-12-12 20:30:09 +00:00
d6b17765e4
remove some never-completed and now-obsolete code.
...
llvm-svn: 24671
2005-12-12 20:12:20 +00:00
e80248b378
Add a few more add / store patterns. e.g. ADD32mi8.
...
llvm-svn: 24670
2005-12-12 19:45:23 +00:00
cdb16ef6f3
Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible.
...
llvm-svn: 24669
2005-12-12 19:37:43 +00:00
b8296181e0
restore a more restricted select
...
llvm-svn: 24668
2005-12-12 17:43:52 +00:00
3b0a62d8a5
Implement a little hack for parity with GCC on crafty. This speeds up
...
186.crafty by about 16% (from 15.109s to 13.045s) on my system.
This turns allocas with unions/casts into scalars. For example crafty has
something like this:
union doub {
unsigned short i[4];
long long d;
};
int f(long long a) {
return ((union doub){.d=a}).i[1];
}
Instead of generating loads and stores to an alloca, we now promote the
whole thing to a scalar long value.
This implements: Transforms/ScalarRepl/AggregatePromote.ll
llvm-svn: 24667
2005-12-12 07:19:13 +00:00
cf510b36c1
new testcase: sra should be able to eliminate all of these alloca's, despite
...
the presense of pointer casts
llvm-svn: 24666
2005-12-12 07:18:59 +00:00
08dbd94632
Send an indicator to llvm-testresults if the build failed
...
llvm-svn: 24665
2005-12-11 19:55:39 +00:00
a4c6cc5af4
Fix typo :(
...
llvm-svn: 24664
2005-12-11 18:43:13 +00:00
f1a54c0d14
Minor tweak to get isel opt
...
llvm-svn: 24663
2005-12-11 09:05:13 +00:00
254e0a842f
add selectcc
...
llvm-svn: 24662
2005-12-11 08:35:54 +00:00
090eed0483
Remove type casts that are no longer needed
...
llvm-svn: 24661
2005-12-11 07:45:47 +00:00
e6f2c82073
Realize the constant pool & global addrs must always be ptr type
...
llvm-svn: 24660
2005-12-11 07:45:04 +00:00
3d9559fedc
Fix the JIT failures from last night.
...
llvm-svn: 24659
2005-12-11 07:37:41 +00:00
20d0b81c04
FP select improvements (and likely breakage), oh and crazy people might want to *return* floating point values. Don't see why myself
...
llvm-svn: 24658
2005-12-11 03:54:31 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
3c5198336c
Use SDTCisPtrTy type property for store address.
...
llvm-svn: 24656
2005-12-10 01:59:36 +00:00
0da396ffe2
Stop emitting a redudant type check for complex pattern node.
...
llvm-svn: 24655
2005-12-10 01:57:33 +00:00
0d6cfee704
* Added X86 store patterns.
...
* Added X86 dec patterns.
llvm-svn: 24654
2005-12-10 00:48:20 +00:00
dadc1057ac
Added new getNode and getTargetNode variants for X86 stores.
...
llvm-svn: 24653
2005-12-10 00:37:58 +00:00
bac252c289
For instructions which produce no result, e.g. store, chain's Resno == 0.
...
llvm-svn: 24652
2005-12-10 00:09:17 +00:00
ade6f9a255
Add support patterns to many load and store instructions which will
...
hopefully use patterns in the near future.
llvm-svn: 24651
2005-12-09 23:54:18 +00:00
27656ac89c
Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load
...
must be a pointer. This removes a type check out of the code generated by
tblgen for load matching.
llvm-svn: 24650
2005-12-09 22:58:42 +00:00
433573f4c6
Add a new SDTCisPtrTy constraint, which indicates that an operand must have
...
the same type as the pointer type for a target.
llvm-svn: 24649
2005-12-09 22:57:42 +00:00
275a3ed80c
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
...
llvm-svn: 24648
2005-12-09 22:48:48 +00:00
499ab2a9fa
* Do not allow nodes which produce chain results (e.g. loads) to be folded if
...
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
llvm-svn: 24647
2005-12-09 22:45:35 +00:00
a6f835f5a0
Avoid emitting two tabs when switching to a named section
...
llvm-svn: 24646
2005-12-09 19:28:49 +00:00
e0f5f8e43c
Teach the PPC backend about the ctor and dtor list when not using __main and
...
linking the entire program into one bc file.
llvm-svn: 24645
2005-12-09 18:24:29 +00:00
268d457b69
Teach legalize how to promote sext_inreg to fix a problem Andrew pointed
...
out to me.
llvm-svn: 24644
2005-12-09 17:32:47 +00:00
c1f911a238
Prevent folding of instructions which produce chains that have more than 1 real use
...
llvm-svn: 24643
2005-12-09 06:06:08 +00:00
f423a17e33
* Make sure complex pattern operands are selected first since their select
...
functions can return false and causing the instruction pattern match to fail.
* Code clean up.
llvm-svn: 24642
2005-12-09 00:48:42 +00:00
87bf2234b5
it helps if your conditionals are not reversed
...
llvm-svn: 24641
2005-12-09 00:45:42 +00:00
be73d6eece
improve code insertion in two ways:
...
1. Only forward subst offsets into loads and stores, not into arbitrary
things, where it will likely become a load.
2. If the source is a cast from pointer, forward subst the cast as well,
allowing us to fold the cast away (improving cases when the cast is
from an alloca or global).
This hasn't been fully tested, but does appear to further reduce register
pressure and improve code. Lets let the testers grind on it a bit. :)
llvm-svn: 24640
2005-12-08 08:00:12 +00:00
29e6c3dbf9
Add another important case we miss
...
llvm-svn: 24639
2005-12-08 07:13:28 +00:00
790af6d18f
Added support for ComplexPattern.
...
llvm-svn: 24638
2005-12-08 04:28:48 +00:00
f039648614
Added explicit type field to ComplexPattern.
...
llvm-svn: 24637
2005-12-08 02:15:07 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
...
* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
c9fab31098
* Added intelligence to X86 LEA addressing mode matching routine so it returns
...
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
llvm-svn: 24635
2005-12-08 02:01:35 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
...
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
ae89d862f5
Fix a crash where ConstantVec nodes were being generated with the wrong
...
type when the target did not support them. Also teach Legalize how to
expand ConstantVecs.
This allows us to generate
_test:
lwz r2, 12(r3)
lwz r4, 8(r3)
lwz r5, 4(r3)
lwz r6, 0(r3)
addi r2, r2, 4
addi r4, r4, 3
addi r5, r5, 2
addi r6, r6, 1
stw r2, 12(r3)
stw r4, 8(r3)
stw r5, 4(r3)
stw r6, 0(r3)
blr
For:
void %test(%v4i *%P) {
%T = load %v4i* %P
%S = add %v4i %T, <int 1, int 2, int 3, int 4>
store %v4i %S, %v4i * %P
ret void
}
On PowerPC.
llvm-svn: 24633
2005-12-07 19:48:11 +00:00
57c882edf8
Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or
...
if the target supports the resultant sextinreg
llvm-svn: 24632
2005-12-07 18:02:05 +00:00
3225733e65
X86 doesn't support sextinreg for 8-bit things either.
...
llvm-svn: 24631
2005-12-07 17:59:14 +00:00
cbd3d01a43
Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg
...
when the types match up. This allows the X86 backend to compile:
sbyte %toggle_value(sbyte* %tmp.1) {
%tmp.2 = load sbyte* %tmp.1
ret sbyte %tmp.2
}
to this:
_toggle_value:
mov %EAX, DWORD PTR [%ESP + 4]
movsx %EAX, BYTE PTR [%EAX]
ret
instead of this:
_toggle_value:
mov %EAX, DWORD PTR [%ESP + 4]
movsx %EAX, BYTE PTR [%EAX]
movsx %EAX, %AL
ret
noticed in Shootout/objinst.
-Chris
llvm-svn: 24630
2005-12-07 07:11:03 +00:00
30aa5f735f
Remove a now-dead map, patch by Saem Ghani, thanks!
...
llvm-svn: 24629
2005-12-07 05:41:44 +00:00
26473b6b58
fix divide and remainder
...
llvm-svn: 24628
2005-12-06 23:27:39 +00:00
de085f0165
Silence another annoying GCC warning
...
llvm-svn: 24627
2005-12-06 20:56:18 +00:00
312e65568c
This solves the problem of the CBE renaming symbols that start with . but the assembly side still trying to reference them by their old names. Should be safe untill we hit a language front end that lets you specify such a name.
...
llvm-svn: 24626
2005-12-06 20:51:30 +00:00
Chris Lattner