9cc324d31a
ARM some VFP tblgen'erated two-operand aliases.
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llvm-svn: 155178
2012-04-20 00:15:00 +00:00
5efc442290
Add more fused mul+add/sub patterns. rdar://10139676
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llvm-svn: 154484
2012-04-11 06:59:47 +00:00
48346c1cd9
Clean up ARM fused multiply + add/sub support some more: rename some isel
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predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?
rdar://10139676
llvm-svn: 154480
2012-04-11 05:33:07 +00:00
67a09fc397
Match (fneg (fma) to vfnma. rdar://10139676
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llvm-svn: 154469
2012-04-11 01:21:25 +00:00
d0007f3c83
Handle llvm.fma.* intrinsics. rdar://10914096
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llvm-svn: 154439
2012-04-10 21:40:28 +00:00
db7db7d3a3
ARM divided syntax fmrx/fmxr mnemonics.
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llvm-svn: 152946
2012-03-16 21:06:13 +00:00
24d90e2ddc
ARM vmrs system registers mvfr0 and mvfr1 handling.
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rdar://11058464
llvm-svn: 152881
2012-03-16 00:27:18 +00:00
d28888dd77
ARM case-insensitive checking for APSR_nzcv.
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rdar://11056591
llvm-svn: 152846
2012-03-15 21:34:14 +00:00
d74560b170
ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.
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rdar://11056647
llvm-svn: 152834
2012-03-15 20:48:18 +00:00
327d2f9da5
Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
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llvm-svn: 152814
2012-03-15 17:50:29 +00:00
718cfbe05a
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
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The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
llvm-svn: 152076
2012-03-06 00:19:55 +00:00
8dc347fc27
ARM vpush/vpop assembler mnemonics accept an optional size suffix.
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rdar://10988114
llvm-svn: 152068
2012-03-05 23:16:31 +00:00
957a6583f1
updated patch for the ARM fused multiply add/sub
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In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.
Patch by Ana Pazos <apazos@codeaurora.org>
llvm-svn: 152036
2012-03-05 17:39:52 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
5482b9f535
Add fused multiple+add instructions from VFPv4.
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Patch by Ana Pazos!
llvm-svn: 148658
2012-01-22 12:07:33 +00:00
ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
b65dd04923
Remove some bogus comments.
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llvm-svn: 147169
2011-12-22 19:45:01 +00:00
489ed5929e
ARM pre-UAL aliases. fcmp[sd].
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llvm-svn: 147158
2011-12-22 19:20:45 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
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llvm-svn: 147104
2011-12-21 23:24:15 +00:00
e16acacc3a
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
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llvm-svn: 146892
2011-12-19 19:43:50 +00:00
92a939ae73
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
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llvm-svn: 146887
2011-12-19 19:02:41 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
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llvm-svn: 146514
2011-12-13 20:40:37 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146508
2011-12-13 20:13:48 +00:00
9227f39c53
ARM add more 'gas' compatibility aliases for NEON instructions.
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llvm-svn: 146507
2011-12-13 20:08:32 +00:00
54337b8617
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146300
2011-12-10 00:01:02 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146296
2011-12-09 23:34:09 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
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llvm-svn: 146201
2011-12-08 22:51:25 +00:00
9a6ba3c94e
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
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llvm-svn: 146116
2011-12-08 00:52:55 +00:00
086d013e56
ARM VFP support 'flds/fldd' aliases for 'vldr'
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llvm-svn: 146115
2011-12-08 00:49:29 +00:00
2cf294a213
ARM tidy up and remove no longer needed InstAlias definitions.
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The TokenAlias handling of data type suffices renders these unnecessary.
llvm-svn: 146010
2011-12-07 01:50:36 +00:00
a01033709f
ARM VFP assembly parsing for VADD and VSUB two-operand forms.
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llvm-svn: 144710
2011-11-15 22:15:10 +00:00
84f0ba5747
ARM size suffix on VFP single-precision 'vmov' is optional.
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rdar://10435114
llvm-svn: 144698
2011-11-15 21:18:35 +00:00
5803f6d5a2
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
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Yet more of rdar://10435076.
llvm-svn: 144691
2011-11-15 20:29:42 +00:00
c5b1bc561e
ARM assembly parsing for two-operand form of 'mul' instruction.
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rdar://10449856.
llvm-svn: 144689
2011-11-15 20:14:51 +00:00
3e2c6f380c
ARM VLDR/VSTR instructions don't need a size suffix.
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Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
7996b15724
ARM assembly parsing type suffix options for VLDR/VSTR.
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rdar://10435076
llvm-svn: 144575
2011-11-14 22:28:39 +00:00
609d113874
ARM optional size suffix for VLDR/VSTR syntax.
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llvm-svn: 144427
2011-11-11 23:34:43 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
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llvm-svn: 141046
2011-10-03 23:38:36 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
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llvm-svn: 141025
2011-10-03 21:12:43 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
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Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
3e0aa03fe9
Add missing encoding information for some of the GPR<->FP register moves.
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llvm-svn: 138780
2011-08-29 23:15:25 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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llvm-svn: 138273
2011-08-22 21:34:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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llvm-svn: 138269
2011-08-22 20:27:12 +00:00
713406f88d
Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
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llvm-svn: 136707
2011-08-02 18:30:00 +00:00
651b230ca0
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
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llvm-svn: 135106
2011-07-13 23:22:26 +00:00
148220306f
The VMLA instruction and its friends are not actually fused; they're plain old
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multiply-accumulate instructions with separate rounding steps.
llvm-svn: 134609
2011-07-07 08:28:52 +00:00
29882a75eb
ARM assembler support for vpush/vpop.
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Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.
rdar://9683231
llvm-svn: 133932
2011-06-27 20:00:07 +00:00
7ef7ddd2df
Clean up a few 80 column violations.
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llvm-svn: 132946
2011-06-13 22:54:22 +00:00
3e5944d96b
Some single-precision VFP instructions can execute in either the VPF or Neon
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pipelines, at least on Cortex-A9.
llvm-svn: 129771
2011-04-19 18:11:38 +00:00
d6c5a741b5
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
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llvm-svn: 128461
2011-03-29 16:45:53 +00:00
Jim Grosbach