5b5c953b07
ISB is HasDB, not just HasV7.
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llvm-svn: 139202
2011-09-06 23:09:19 +00:00
83a6188f18
Thumb2 parsing and encoding for ISB.
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llvm-svn: 139200
2011-09-06 22:53:27 +00:00
958feffa11
Thumb2 parsing and encoding for EOR.
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llvm-svn: 139199
2011-09-06 22:44:50 +00:00
ed9399995a
Thumb2 parsing and encoding for DSB.
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llvm-svn: 139194
2011-09-06 22:19:40 +00:00
e95f46384e
Thumb2 parsing and encoding for DMB.
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llvm-svn: 139193
2011-09-06 22:14:58 +00:00
474c455060
Disable these tests harder. They're XFAIL'd, but that means they still run, and
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these tests all infinitely recurse, bringing my system down into swapping hell.
llvm-svn: 139192
2011-09-06 22:08:18 +00:00
c048b905b4
Thumb2 parsing and encoding for DBG.
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llvm-svn: 139191
2011-09-06 22:06:40 +00:00
565e2f5752
Thumb2 parsing and encoding for CMN and CMP.
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llvm-svn: 139188
2011-09-06 21:44:58 +00:00
e0aa54bb98
This transform only handles two-operand AddRec's. Prevent it from trying to
...
handle anything more complex. Fixes PR10383 again!
llvm-svn: 139186
2011-09-06 21:42:18 +00:00
fc4b343dda
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
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llvm-svn: 139179
2011-09-06 20:53:37 +00:00
70532e289f
Thumb2 parsing and encoding for CLZ.
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llvm-svn: 139177
2011-09-06 20:44:17 +00:00
803898f119
Thumb2 parsing and encoding for CLREX.
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llvm-svn: 139172
2011-09-06 20:27:04 +00:00
b041e866b0
Port more encoding tests over to Thumb2 decoding tests.
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llvm-svn: 139171
2011-09-06 20:26:34 +00:00
1eee7f1242
Add -verify-indvars for imperfect SCEV trip count verification after indvars.
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llvm-svn: 139169
2011-09-06 20:20:38 +00:00
6952281037
Thumb2 parsing and encoding for CDP/CDP2.
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llvm-svn: 139168
2011-09-06 20:12:23 +00:00
9d96c94278
Fix comment. Noticed by Duncan.
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llvm-svn: 139161
2011-09-06 19:29:31 +00:00
f2641e1bc1
Add codegen support for vector select (in the IR this means a select
...
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
2011-09-06 19:07:46 +00:00
0b758ed6ba
Fix fall outs from my recent change on how carry bit is modeled during isel.
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Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
llvm-svn: 139157
2011-09-06 18:52:20 +00:00
c10e52a0c4
Use IRBuilder.
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llvm-svn: 139156
2011-09-06 18:49:53 +00:00
f471ac3c72
ARM .code directive should always go to the streamer.
...
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).
llvm-svn: 139155
2011-09-06 18:46:23 +00:00
db5823dc77
Fix style issues and typos found by Duncan.
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llvm-svn: 139154
2011-09-06 18:43:08 +00:00
9803abb788
As a first step, emit both the compact unwind and CIE/FDEs for a function.
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llvm-svn: 139152
2011-09-06 18:37:11 +00:00
58704ee442
Try again at r138809 (make DSE more aggressive in removing dead stores at the end of a function), now with less deleting stores before memcpy's.
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llvm-svn: 139150
2011-09-06 18:14:09 +00:00
50ef7611aa
Atomic pseudos don't use (as in read) CPSR. They clobber it.
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llvm-svn: 139148
2011-09-06 17:40:35 +00:00
5ea5d7965b
Now, named mdnode llvm.dbg.cu keeps track of all compile units in a module. Update DebugInfoFinder to collect compile units from llvm.dbg.cu.
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llvm-svn: 139147
2011-09-06 17:40:08 +00:00
a098436b32
Split the init.trampoline intrinsic, which currently combines GCC's
...
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
llvm-svn: 139140
2011-09-06 13:37:06 +00:00
78664db054
Fix typo in comment again.
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llvm-svn: 139139
2011-09-06 07:02:40 +00:00
237878b7ac
Apparently we compile the code, not the comments. Thanks Eli!
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llvm-svn: 139138
2011-09-06 06:56:00 +00:00
0af94cc50b
Fix typo in comment.
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llvm-svn: 139137
2011-09-06 06:46:01 +00:00
702cf1eccc
Nope! I had it right the first time. Revert the operative part of r139135 and
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add more showing of my work.
llvm-svn: 139136
2011-09-06 06:39:54 +00:00
6f86e001d6
Fix flipped sign. While there, show my math.
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llvm-svn: 139135
2011-09-06 05:33:18 +00:00
db66b82dd5
No no no, fix typo properly!
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llvm-svn: 139134
2011-09-06 05:08:09 +00:00
658bdb5133
The logic inside getMulExpr to simplify {a,+,b}*{c,+,d} was wrong, which was
...
visible given a=b=c=d=1, on iteration #1 (the second iteration). Replace it with
correct math. Fixes PR10383!
llvm-svn: 139133
2011-09-06 05:05:14 +00:00
b1438c763a
Revert r139126 due to selfhost failures reported by buildbots.
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llvm-svn: 139130
2011-09-06 02:43:13 +00:00
c4c43fbb07
Teach SCEV to report a max backedge count in one interesting case in
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HowFarToZero; the case for a canonical loop.
llvm-svn: 139126
2011-09-05 23:25:16 +00:00
73df7e3830
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
...
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
llvm-svn: 139125
2011-09-05 21:51:43 +00:00
df06b6e069
Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger!
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llvm-svn: 139124
2011-09-05 18:50:59 +00:00
f1a5f57d2f
Fix typo in comment.
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llvm-svn: 139122
2011-09-05 18:35:03 +00:00
4b79c21ef2
InstSimplify: Don't try to replace an extractvalue/insertvalue pair with the original value if types don't match.
...
Fixes clang selfhost.
llvm-svn: 139120
2011-09-05 18:16:19 +00:00
29192d042e
Delete trivial landing pads that just continue unwinding the caught
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exception.
llvm-svn: 139117
2011-09-05 12:57:57 +00:00
fd26a954a8
Add some simple insertvalue simplifications, for the purpose of cleaning
...
up do-nothing exception handling code produced by dragonegg.
llvm-svn: 139113
2011-09-05 06:52:48 +00:00
0ca1ad0783
Use canonical forms for the branch probability zero heutistic.
...
- Drop support for X >u 0, it's equivalent to X != 0 and should be canonicalized into the latter.
- Add X < 1 -> unlikely, which is what instcombine canonicalizes X <= 0 into.
- Add X > -1 -> likely, which is what instcombine canonicalizes X >= 0 into.
llvm-svn: 139110
2011-09-04 23:53:04 +00:00
908abc3439
As a (rather delayed) followup to r136738 which stopped building the
...
edis shared library in the Makefile build, also stop building it in the
CMake build.
Patch by arrowdodger!
llvm-svn: 139108
2011-09-04 23:32:05 +00:00
ada9aa2b98
Complete the removal of FindBison from CMake. Noticed this when browsing
...
some CMake patch backlog...
llvm-svn: 139107
2011-09-04 23:29:12 +00:00
ceb4e6408a
Update the CMake documentation to the correct variables.
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Patch by arrowdodger!
llvm-svn: 139106
2011-09-04 23:24:13 +00:00
321fb37773
Use Duncan's patch to delete the instructions in reverse order (minus the landingpad and terminator).
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llvm-svn: 139090
2011-09-04 09:43:36 +00:00
acaad83cd0
The insertion point for the loads is right before the llvm.eh.exception
...
call. The call may be in the same BB as the landingpad instruction. If that's
the case, then inserting the loads after the landingpad inst, but before the
extractvalues, causes undefined behavior.
llvm-svn: 139088
2011-09-04 09:02:18 +00:00
09ade9bb8b
valgrind: Suppress glibc's optiized strcasecmp harder.
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llvm-svn: 139084
2011-09-03 17:59:31 +00:00
7859d2e148
Use internal storage for command line option.
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llvm-svn: 139079
2011-09-03 03:45:06 +00:00
7c1d6358a2
Don't reload the values that are already there. The llvm.eh.resume uses the same
...
values that the resume instruction uses.
PR10850
llvm-svn: 139076
2011-09-03 01:38:17 +00:00
2f5420b225
Exclude more arm jit failures pending PR10783.
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llvm-svn: 139074
2011-09-03 01:08:35 +00:00
07d9914620
Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends
...
the cycle of missing AVX counterparts of already present SSE* patterns
llvm-svn: 139073
2011-09-03 00:47:08 +00:00
1d5c2d9227
Add AVX version of a SSE4.1 VPBLENDVB pattern
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llvm-svn: 139072
2011-09-03 00:47:05 +00:00
212a8c4357
Add AVX versions of SSE4.1 EXTRACTPS patterns
...
llvm-svn: 139071
2011-09-03 00:47:03 +00:00
3d581a36b6
Add AVX versions for SSE4.1 MOVZX* patterns
...
llvm-svn: 139070
2011-09-03 00:47:01 +00:00
6d701fcef0
Add one more AVX pattern for MOVZPQILo2PQI
...
llvm-svn: 139069
2011-09-03 00:46:58 +00:00
9923c51564
Move PUNPCKLQDQ splat pattern close to the instruction definition and
...
duplicate it for AVX mode.
llvm-svn: 139068
2011-09-03 00:46:56 +00:00
96b11f39e2
Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
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llvm-svn: 139067
2011-09-03 00:46:54 +00:00
9a0da1e57a
Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate
...
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.
llvm-svn: 139066
2011-09-03 00:46:51 +00:00
903952223a
Enforce subtarget checks in a few places to be explicit when the
...
pattern should be matched
llvm-svn: 139065
2011-09-03 00:46:49 +00:00
521b0cfdc6
Tidy up code moving patterns to their appropriate place!
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llvm-svn: 139064
2011-09-03 00:46:47 +00:00
aad5e50ded
Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
...
it!
llvm-svn: 139063
2011-09-03 00:46:45 +00:00
d893fc92af
Teach X86FastISel to use AVX versions of instructions when possible
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llvm-svn: 139062
2011-09-03 00:46:42 +00:00
006c9371a1
Fix 80-column and style
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llvm-svn: 139061
2011-09-03 00:46:40 +00:00
dbb40015ff
Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of
...
OptForSize pattern
llvm-svn: 139060
2011-09-03 00:46:38 +00:00
40d756eacc
Fix a truly heinous bug in DAGCombine related to AssertZext.
...
If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.
llvm-svn: 139059
2011-09-03 00:26:49 +00:00
5423017526
Revert r129875, XFAILing this test for arm, since the fix was reverted.
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llvm-svn: 139058
2011-09-03 00:14:24 +00:00
1f72dd40c7
Pseudo CMOV instructions don't clobber EFLAGS.
...
The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
llvm-svn: 139057
2011-09-02 23:52:55 +00:00
f08354d183
Check for EFLAGS live-out before clobbering it.
...
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.
llvm-svn: 139056
2011-09-02 23:52:52 +00:00
d0c8a31c8b
Use existing function.
...
llvm-svn: 139055
2011-09-02 23:52:49 +00:00
f347d1d772
Thumb2 parsing and encoding for CBZ/CBNZ.
...
llvm-svn: 139054
2011-09-02 23:46:10 +00:00
34842ceb97
Thumb2 parsing and encoding for BXJ.
...
llvm-svn: 139053
2011-09-02 23:43:09 +00:00
9e55023ca7
Thumb2 parsing and encoding for BIC.
...
llvm-svn: 139052
2011-09-02 23:37:54 +00:00
93e3fd29b2
Thumb2 parsing and encoding for BFI.
...
llvm-svn: 139051
2011-09-02 23:28:46 +00:00
be31448d99
Thumb2 parsing and encoding for BFC.
...
llvm-svn: 139050
2011-09-02 23:25:46 +00:00
a0d34d3b5e
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
67ba2403e8
Attempt to silence known valgrind errors.
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llvm-svn: 139048
2011-09-02 22:59:34 +00:00
38019e3188
Remove unused variables.
...
llvm-svn: 139047
2011-09-02 22:41:25 +00:00
4aa2573748
Try to eliminate the use of the 'unwind' instruction.
...
llvm-svn: 139046
2011-09-02 22:41:11 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
...
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
a216debb37
Thumb2 parsing and encoding for ASR.
...
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
912668d998
Better fix for this testcase. Update it to the new EH scheme entirely.
...
llvm-svn: 139039
2011-09-02 21:27:08 +00:00
17706bcffb
Update for new EH stuff. (I'm not sure if this is 100% correct.)
...
llvm-svn: 139038
2011-09-02 21:24:17 +00:00
310a448cfe
Test case update for unroll-scev.
...
llvm-svn: 139037
2011-09-02 21:21:03 +00:00
bbb226a827
Comment and clarifying assert.
...
llvm-svn: 139036
2011-09-02 21:20:46 +00:00
73e6333ce1
No need to get fancy inserting a PHI node when the values are stored in stack
...
slots. This fixes a bug where the number of nodes coming into the PHI node may
not equal the number of predecessors. E.g., two or more landingpad instructions
may require a PHI before reaching the eh.exception and eh.selector instructions.
llvm-svn: 139035
2011-09-02 21:17:08 +00:00
09d153eb12
Make RecordVal Name an Init
...
Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names. We'll use this to
provide more programmability in how we name defs and their associated
members.
llvm-svn: 139031
2011-09-02 20:12:07 +00:00
5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
05dec8b122
Tidy up. Formatting.
...
llvm-svn: 139024
2011-09-02 18:46:15 +00:00
a336e70573
Update comments to reflect reality.
...
llvm-svn: 139023
2011-09-02 18:43:33 +00:00
0a57375a28
Tidy up. 80 columns.
...
llvm-svn: 139022
2011-09-02 18:43:25 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
...
llvm-svn: 139021
2011-09-02 18:41:35 +00:00
97fe09ad2e
Simplify by using isFullCopy().
...
llvm-svn: 139019
2011-09-02 18:18:29 +00:00
4e1d018935
Revert r138826 until PR10834 can be fixed.
...
llvm-svn: 139018
2011-09-02 18:15:04 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
5c04c62765
Darwin wants ctors/dtors to be ordered the other way round to linux.
...
llvm-svn: 139015
2011-09-02 18:07:19 +00:00
54e09b4799
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
...
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
b861b2b475
Tests for Thumb2 AND (immediate) instruction.
...
llvm-svn: 139013
2011-09-02 17:44:27 +00:00
63a3a0e010
Extra CHECK-NOT to make sure that GVN transform works properly.
...
llvm-svn: 139012
2011-09-02 17:40:39 +00:00
4a31ba3bae
-unroll-scev flag removal
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llvm-svn: 139010
2011-09-02 17:36:14 +00:00
Jim Grosbach