Commit Graph

183 Commits

Author SHA1 Message Date
Craig Topper 8665f59e2c [Support] Stop passing StringRefs by const reference in some of the getHostCPUname implementations. NFC
llvm-svn: 326916
2018-03-07 17:53:16 +00:00
Craig Topper 55ad3299d4 [X86] Fix a typo in Host.cpp that causes us to misidentify KNL, Silvermont, Goldmont and probably other CPUs for -march=native
I think most of the Intel Core CPUs and recent AMD CPUs are unaffected. All the CPUs that have a "subtype" should work. The ones that were broken are the ones that are a "type" with no subtypes.

Fixes PR36619.

llvm-svn: 326840
2018-03-06 22:45:31 +00:00
Craig Topper 8d02be3bf3 [X86] Add 'sahf' to getHostCPUFeatures so -march=native will pick it up correctly.
Summary: We probably mostly get this right due to family/model/stepping mapping to CPU names. But we should detect it explicitly.

Reviewers: RKSimon, echristo, dim, spatel

Reviewed By: dim

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43418

llvm-svn: 325439
2018-02-17 16:52:49 +00:00
Craig Topper 84b26b90d1 [X86] Add intrinsic support for the RDPID instruction
This adds a new instrinsic to support the rdpid instruction. The implementation is a bit weird because the intrinsic is defined as always returning 32-bits, but the assembler support thinks the instruction produces a 64-bit register in 64-bit mode. But really it zeros the upper 32 bits. So I had to add separate patterns where 64-bit mode uses an extract_subreg.

Differential Revision: https://reviews.llvm.org/D42205

llvm-svn: 322910
2018-01-18 23:52:31 +00:00
Craig Topper 48176a5fb6 [X86] Minor formatting fix to getHostCPUFeatures. NFC
llvm-svn: 321015
2017-12-18 19:40:11 +00:00
Evandro Menezes 5d7a9e6e54 [AArch64] Add Exynos to host detection
Differential revision: https://reviews.llvm.org/D40985

llvm-svn: 320195
2017-12-08 21:09:59 +00:00
Oren Ben Simhon fa582b075c Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)
Shadow stack solution introduces a new stack for return addresses only.
The HW has a Shadow Stack Pointer (SSP) that points to the next return address.
If we return to a different address, an exception is triggered.
The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP).
The intrinsics are mapped to new instruction set that implements CET mechanism.

The patch also includes initial infrastructure support for IBT.

For more information, please see the following:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

Differential Revision: https://reviews.llvm.org/D40223

Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4
llvm-svn: 318996
2017-11-26 13:02:45 +00:00
Coby Tayree d8b17bedfa [x86][icelake]GFNI
galois field arithmetic (GF(2^8)) insns:
gf2p8affineinvqb
gf2p8affineqb
gf2p8mulb
Differential Revision: https://reviews.llvm.org/D40373

llvm-svn: 318993
2017-11-26 09:36:41 +00:00
Craig Topper 47c8739b08 [X86] Move the information about the feature bits used by compiler-rt and shared by Host.cpp to a .def file and TargetParser.h so clang can make use of it.
Since we keep Host.cpp and compiler-rt relatively in sync, clang can use this information as a proxy.

llvm-svn: 318814
2017-11-21 23:36:42 +00:00
Craig Topper 9b03f67f9a [X86] Sort bits in getHostCPUFeatures again.
llvm-svn: 318792
2017-11-21 18:50:41 +00:00
Coby Tayree 5c7fe5df53 [x86][icelake]BITALG
vpopcnt{b,w}
Differential Revision: https://reviews.llvm.org/D40213

llvm-svn: 318748
2017-11-21 10:32:42 +00:00
Coby Tayree 3880f2a363 [x86][icelake]VNNI
Introducing Vector Neural Network Instructions, consisting of:
vpdpbusd{s}
vpdpwssd{s}
Differential Revision: https://reviews.llvm.org/D40208

llvm-svn: 318746
2017-11-21 10:04:28 +00:00
Coby Tayree 71e37cc9ff [x86][icelake]vbmi2
introducing vbmi2, consisting of
vpcompress{b,w}
vpexpand{b,w}
vpsh{l,r}d{w,d,q}
vpsh{l,r}dv{w,d,q}
Differential Revision: https://reviews.llvm.org/D40206

llvm-svn: 318745
2017-11-21 09:48:44 +00:00
Coby Tayree 7ca5e58736 [x86][icelake]vpclmulqdq introduction
an icelake promotion of pclmulqdq
Differential Revision: https://reviews.llvm.org/D40101

llvm-svn: 318741
2017-11-21 09:30:33 +00:00
Coby Tayree 2a1c02fcbc [x86][icelake]VAES introduction
an icelake promotion of AES
Differential Revision: https://reviews.llvm.org/D40078

llvm-svn: 318740
2017-11-21 09:11:41 +00:00
Craig Topper dcd69797a6 [X86] clzero check in getHostCPUFeatures should use getX86CpuIDAndInfo not getX86CpuIDAndInfoEx.
This leaf doesn't take an additional argument.

llvm-svn: 318634
2017-11-19 23:49:19 +00:00
Craig Topper 1af7e4424f [X86] Reorder and reformat the feature bit checks in getHostCPUFeatues to keep the bits in order per register and encourage future additions to be in order too.
llvm-svn: 318633
2017-11-19 23:30:22 +00:00
Craig Topper 4a1ec811af [X86] Add some explanatory comments to the ProcessorFeatures enum in Host.cpp.
llvm-svn: 318331
2017-11-15 20:42:49 +00:00
Craig Topper 0dadfe30d2 [X86] Add getHostCPUName support for the Gemini Lake model number which also uses Goldmont.
llvm-svn: 318271
2017-11-15 06:02:43 +00:00
Craig Topper 0749186a70 [X86] Add getHostCPUName support for cannonlake.
This adds an explicit model number check and fallback path to the unknown family 6 detection.

llvm-svn: 318270
2017-11-15 06:02:42 +00:00
Craig Topper c77d00e327 [X86] Add a def file to CPU vendor, type, and subtype encodings used by Host.cpp
Summary:
I want to leverage this to clean up some of the code in clang. This will allow us to simplify D39521 which was trying to do some of the same.

If we accurately keep the code in Host.cpp synced with new CPUs added to compile-rt/libgcc we should be able to use this file as a proxy for what's implemented in the libraries.

The entries for the CPUs recognized by the libraries use separate macros that define additional parameters like the name for __builtin_cpu_is and an alias string for the couple cases where __builtin_cpu_is accepts two different names.

All of the macros contain an ARCHNAME that is usually the same as the __builtin_cpu_is string, but sometimes isn't. This represents the name recognized by X86.td and -march.

I'm following the precedent set by ARM and AArch64 and adding this information to lib/Support/TargetParser.cpp

Reviewers: erichkeane, echristo, asbirlea

Reviewed By: echristo

Subscribers: llvm-commits, aemerson, kristof.beyls

Differential Revision: https://reviews.llvm.org/D39782

llvm-svn: 317900
2017-11-10 17:10:57 +00:00
Craig Topper 8b6600363a [X86] Promote athlon, athlon-xp, k8, and k8-sse3 to types instead of subtypes in getHostCPUName. NFCI
This removes the athlon type and simplifies the string decoding. We only really need these type/subtype breaks where we need to match libgcc/compiler-rt and these CPUs aren't part of that.

I'm looking into moving some of this information to a .def file to share with clang's __builtin_cpu_is handling. And while these CPUs aren't part of that the less lines I have to deal with in the .def file the better.

llvm-svn: 317354
2017-11-03 19:37:41 +00:00
Craig Topper 741e7e6a71 [X86] Initialize Type and Subtype in getHostCPUName to 0.
llvm-svn: 317341
2017-11-03 18:02:44 +00:00
Craig Topper 1494915a3a [X86] Simplify the pentium4 code in getHostCPUName to be based on feature flags. Don't use 'x86-64' ever.
'x86-64' has started to reflect a sort of generic tuning flag for more modern 64-bit CPUs. We probably shouldn't be using it as the name of an unidentifiable pentium4. So use nocona for all 64-bit pentium4s instead.

llvm-svn: 317230
2017-11-02 19:13:34 +00:00
Craig Topper a233e16cd8 [X86] Change getHostCPUName fallback code to not select 'x86-64' for unknown CPUs in family 6 that has 64-bit support but not any newer SSE features. Use 'core2' instead
We know that's the earliest CPU with 64-bit support. x86-64 has taken on a role of representing a more modern 64-bit CPU so we probably shouldn't be using that when we can't identify things.

llvm-svn: 317229
2017-11-02 19:13:32 +00:00
Craig Topper 3bbe24c3ca [X86] Remove the model checks from the 486 detection code in Host.cpp
This just provided a bunch of comments to read and not much else.

llvm-svn: 317185
2017-11-02 03:32:50 +00:00
Craig Topper 094d7914ae [X86] Simplify the detection of pentium-mmx in Host.cpp.
Rather than looking at model numbers just check for the mmx feature flag. While there promote INTEL_PENTIUM_MMX to a CPU type instead of a subtype so that we don't have weird type with only one subtype.

llvm-svn: 317184
2017-11-02 03:32:49 +00:00
Craig Topper 5d692917f4 [X86] Add initial skeleton support for knm cpu
This adds Intel's Knights Mill CPU to valid CPU names for the backend. For now its an alias of "knl", but ultimately we need to support AVX5124FMAPS and AVX5124VNNIW instruction sets for it.

Differential Revision: https://reviews.llvm.org/D38811

llvm-svn: 315722
2017-10-13 18:10:17 +00:00
Chad Rosier 71070856e6 [AArch64] Add basic support for Qualcomm's Saphira CPU.
llvm-svn: 314105
2017-09-25 14:05:00 +00:00
Balaram Makam a1e7ecc734 [Falkor] Add falkor CPU to host detection
This returns "falkor" for Falkor CPU.

llvm-svn: 313998
2017-09-22 17:46:36 +00:00
Eli Friedman bde9fc76dd [ARM] Add more CPUs to host detection
This returns "cortex-a73" for second-generation Kryo; not precisely
correct, but close enough.

Differential Revision: https://reviews.llvm.org/D37724

llvm-svn: 313200
2017-09-13 21:48:00 +00:00
Yonghong Song c6d2571031 bpf: close the file descriptor after probe inside getHostCPUNameForBPF
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 311567
2017-08-23 16:24:31 +00:00
Yonghong Song dc1dbf6ef3 bpf: add variants of -mcpu=# and support for additional jmp insns
-mcpu=# will support:
  . generic: the default insn set
  . v1: insn set version 1, the same as generic
  . v2: insn set version 2, version 1 + additional jmp insns
  . probe: the compiler will probe the underlying kernel to
           decide proper version of insn set.

We did not not use -mcpu=native since llc/llvm will interpret -mcpu=native
as the underlying hardware architecture regardless of -march value.

Currently, only x86_64 supports -mcpu=probe. Other architecture will
silently revert to "generic".

Also added -mcpu=help to print available cpu parameters.
llvm will print out the information only if there are at least one
cpu and at least one feature. Add an unused dummy feature to
enable the printout.

Examples for usage:
$ llc -march=bpf -mcpu=v1 -filetype=asm t.ll
$ llc -march=bpf -mcpu=v2 -filetype=asm t.ll
$ llc -march=bpf -mcpu=generic -filetype=asm t.ll
$ llc -march=bpf -mcpu=probe -filetype=asm t.ll
$ llc -march=bpf -mcpu=v3 -filetype=asm t.ll
'v3' is not a recognized processor for this target (ignoring processor)
...
$ llc -march=bpf -mcpu=help -filetype=asm t.ll
Available CPUs for this target:

  generic - Select the generic processor.
  probe   - Select the probe processor.
  v1      - Select the v1 processor.
  v2      - Select the v2 processor.

Available features for this target:

  dummy - unused feature.

Use +feature to enable a feature, or -feature to disable it.
For example, llc -mcpu=mycpu -mattr=+feature1,-feature2
...

Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 311522
2017-08-23 04:25:57 +00:00
Craig Topper 4eda7561b3 [X86] Improve the unknown stepping support for Intel CPUs in getHostCPUName
This patch improves our guessing of unknown Intel CPUs to support Goldmont and skylake-avx512.

Differential Revision: https://reviews.llvm.org/D35161

llvm-svn: 309246
2017-07-27 03:26:52 +00:00
Ulrich Weigand 2b3482fe85 [SystemZ] Add support for IBM z14 processor (1/3)
This patch series adds support for the IBM z14 processor.  This part includes:
- Basic support for the new processor and its features.
- Support for new instructions (except vector 32-bit float and 128-bit float).
- CodeGen for new instructions, including new LLVM intrinsics.
- Scheduler description for the new processor.
- Detection of z14 as host processor.

Support for the new 32-bit vector float and 128-bit vector float
instructions is provided by separate patches.

llvm-svn: 308194
2017-07-17 17:41:11 +00:00
Craig Topper 828cf302ec [X86] Use MSVC's __cpuidex intrinsic instead of inline assembly in getHostCPUName/getHostCPUFeatures for 32-bit builds too.
We're already using it in 64-bit builds because 64-bit MSVC doesn't support inline assembly.

As far as I know we were using inline assembly because at the time the code was added we had to support MSVC 2008 pre-SP1 while the intrinsic was added to MSVC in SP1. Now that we don't have to support that we should be able to just use the intrinsic.

llvm-svn: 308163
2017-07-17 05:16:16 +00:00
Craig Topper f3de5eb7c6 [X86] Simplify the getHostCPUName for AMD family 6 and 15.
As far as I can tell we can simply distinguish based on features rather than model number. Many of the strings we were previously using are treated the same by the backend.

llvm-svn: 307884
2017-07-13 06:34:10 +00:00
Craig Topper 3a5d082a05 [X86] Synchronize the ProcessorFeatures enum used by getHostCPUName with the enum in libgcc and soon compiler-rt.
This adds all the feature bits libgcc has. They will soon be added to compiler-rt as well. This adds a second 32 bit feature variable to hold the bits that are needed by getHostCPUName that are not in libgcc. libgcc had already used 31 of the 32 bits in the existing variable and we needed 3 bits so at minimum 2 bits would spill over. I chose to move all 3.

llvm-svn: 307758
2017-07-12 06:49:58 +00:00
Craig Topper f3af64e824 [X86] Sync ProcessorTypes and ProcessorSubtypes enums used by getHostCPUName with the version proposed to for compiler-rt's cpu_model.c
This keeps the starting entries in the enums in sync with what's in gcc and in review D35214 for compiler-rt.

llvm-svn: 307757
2017-07-12 06:49:57 +00:00
Craig Topper 3db11705f5 [X86] Cleanup the switches in getHostCPUName to remove impossible combinations.
llvm-svn: 307756
2017-07-12 06:49:56 +00:00
Craig Topper e98b65b809 [X86] Remove 'barcelona' string from getHostCPUName. Use 'amdfam10' instead. The x86 backend doesn't distinguish.
llvm-svn: 307755
2017-07-12 06:49:55 +00:00
Craig Topper ada983a555 [X86] Fix typo in comment. NFC
llvm-svn: 307522
2017-07-10 06:09:22 +00:00
Craig Topper 1efd10ab75 [X86] Remove asserts from getX86CpuIDAndInfo/getX86CpuIDAndInfoEx. Restore past behavior of returning an unsupported indication to the caller instead.
These asserts could only occur if we fail to properly detect the compiler, but an assert is not a good way to do that because it doesn't work in release builds.

I wonder if we could use #error?

llvm-svn: 307520
2017-07-10 06:04:11 +00:00
Craig Topper 52cec3894a [X86] Remove check for AVX512 support from skylake-avx512 detection in getHostCPUName.
Users of getHostCPUName should also use getHostCPUFeatures which will take care of making sure avx512 is disabled if the CPU doesn't support it. This is consistent with what we do for other CPUs.

llvm-svn: 307495
2017-07-09 07:26:14 +00:00
Craig Topper ffe672d200 [X86] In getHostCPUName, remove some code that changes some AMD CPU names based on features not being enabled.
The CPU name is really just used for scheduler and other microarchitectural optimizations. The feature flags should be determined by getHostCPUFeatures which should always be used with getHostCPUName. Trying to alter CPU name strings to control features just isn't practical.

Most of these types of things were removed from Intel CPUs a while ago.

This is part of my plan to bring compiler-rt's cpu_model.c file up to date with the equivalent functionality in libgcc. A lot of the code in that file is copied from Host.cpp and we want to keep them reasonably in sync.

llvm-svn: 307467
2017-07-08 06:44:36 +00:00
Craig Topper 1f9d3c0612 [X86] Correct the BDVER4 model numbers to include 0x70-0x7f.
According to wikipedia and some other googling suggests these should also be considered as BDVER4.

llvm-svn: 307466
2017-07-08 06:44:35 +00:00
Craig Topper 2ace153a82 [X86] Minor formatting fix. NFC
llvm-svn: 307465
2017-07-08 06:44:34 +00:00
Craig Topper c6bbe4becb [X86] Use 'unsigned' instead of 'unsigned int' for consistency in the X86 portion of Host.cpp.
llvm-svn: 307463
2017-07-08 05:16:14 +00:00
Craig Topper bb8c799e1a [X86] Cleanup some CPUID usage in getAvailableFeatures.
We should make sure leaf 1 is available before accessing it. Same with leaf 0x80000001.

llvm-svn: 307462
2017-07-08 05:16:13 +00:00
Alex Lorenz 3803df3dcd [Support] sys::getProcessTriple should return a macOS triple using
the system's version of macOS

sys::getProcessTriple returns LLVM_HOST_TRIPLE, whose system version might not
be the actual version of the system on which the compiler running. This commit
ensures that, for macOS, sys::getProcessTriple returns a triple with the
system's macOS version.

rdar://33177551

Differential Revision: https://reviews.llvm.org/D34446

llvm-svn: 307372
2017-07-07 09:53:47 +00:00