Commit Graph

64113 Commits

Author SHA1 Message Date
Tom Stellard 7f6fa4c4c5 R600: Don't use trans slot for instructions that read LDS source registers
This fixes some regressions in the piglit local memory store tests
introduced by recent commits which made the scheduler aware of the trans
slot.

It's not possible to test this using lit, because there is no way to
determine from the assembly dumps whether or not an instruction is in
the trans slot.

Even if this were possible, the test would be highly sensitive to
changes in the scheduler and might generate confusing false negatives.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 190574
2013-09-12 02:55:06 +00:00
Matt Arsenault bed5bf2e90 Move variable under condition where it is used
llvm-svn: 190567
2013-09-12 01:07:58 +00:00
Matt Arsenault bc08ddba58 Remove pointless assertion after r190376
llvm-svn: 190565
2013-09-12 01:07:49 +00:00
Hal Finkel f574c27769 Greatly simplify the PPC A2 scheduling itinerary
As Andy pointed out to me a long time ago, there are no structural hazards in
the later pipeline stages of the A2, and so modeling them is useless. Also,
modeling the top pre-dispatch stages is deceiving because, when multiple
hardware threads are active, those resources are shared among the threads. The
bypass definitions were mostly wrong, and so those have been removed. The
resulting itinerary is much simpler, and more accurate.

llvm-svn: 190562
2013-09-11 23:25:21 +00:00
Hal Finkel 21442b24fb Enable MI scheduling (and CodeGen AA) by default for embedded PPC cores
For embedded PPC cores (especially the A2 core), using the MI scheduler with AA
is far superior to the other scheduling options.

llvm-svn: 190558
2013-09-11 23:05:25 +00:00
Bill Wendling 7b650a751f Use the appropriate return type for the compact unwind encoding.
llvm-svn: 190551
2013-09-11 21:47:57 +00:00
Hal Finkel 71780ec4fd Implement TTI getUnrollingPreferences for PowerPC
The PowerPC A2 core greatly benefits from aggressive concatenation unrolling;
use the new getUnrollingPreferences to enable this by default when targeting
the PPC A2 core.

llvm-svn: 190549
2013-09-11 21:20:40 +00:00
Bill Wendling 184d5d31bc Move into an anonymous namespace and closer to where it's used.
llvm-svn: 190547
2013-09-11 20:38:09 +00:00
Manman Ren 5b2f4b0540 Debug info: add more comments.
llvm-svn: 190544
2013-09-11 19:40:28 +00:00
Hal Finkel 8f2e700522 Add getUnrollingPreferences to TTI
Allow targets to customize the default behavior of the generic loop unrolling
transformation. This will be used by the PowerPC backend when targeting the A2
core (which is in-order with a deep pipeline), and using more aggressive
defaults is important.

llvm-svn: 190542
2013-09-11 19:25:43 +00:00
Manman Ren fa7b0b8767 Debug Info: move class definition of DIRef.
Definition of DIRef used to require the full definition of DIType because
of usage of DIType::isType in DIRef::resolve. We now use DIDescriptor::isType
instead to remove the requirement and move definition of DIRef before DIType.

With this, we can move the definition of DIType::getContext to the header
file.

llvm-svn: 190540
2013-09-11 18:55:55 +00:00
Benjamin Kramer 079b96e6f7 Revert "Give internal classes hidden visibility."
It works with clang, but GCC has different rules so we can't make all of those
hidden. This reverts commit r190534.

llvm-svn: 190536
2013-09-11 18:05:11 +00:00
Benjamin Kramer 6a44af3629 Give internal classes hidden visibility.
Worth 100k on a linux/x86_64 Release+Asserts clang.

llvm-svn: 190534
2013-09-11 17:42:27 +00:00
Benjamin Kramer fcb7166404 Don't expose symbols of lle_ functions.
+ formatting fixes.

llvm-svn: 190523
2013-09-11 12:42:39 +00:00
Daniel Sanders fbcb582942 [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics)
llvm-svn: 190518
2013-09-11 11:58:30 +00:00
Daniel Sanders f5bd937bc4 [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics)
llvm-svn: 190512
2013-09-11 10:51:30 +00:00
Benjamin Kramer bd4ac9bc6d Path: Add an in-place version of path::native.
This reflects the common use case of nativizing a prepared path. The existing
version invokes undefined behavior if input = output, add an assert to catch
that case.

llvm-svn: 190510
2013-09-11 10:45:21 +00:00
Daniel Sanders 607952bdad [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
llvm-svn: 190509
2013-09-11 10:38:58 +00:00
Daniel Sanders fa5ab1c856 [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.

llvm-svn: 190507
2013-09-11 10:28:16 +00:00
Daniel Sanders c65f58a9c7 [mips][msa] Separate the configuration of int/float vector types since they will diverge soon
No functional change

llvm-svn: 190506
2013-09-11 10:15:48 +00:00
Daniel Sanders cb2929c239 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
2013-09-11 09:59:17 +00:00
Bill Wendling 62a2d14ac5 Simplify the checking of function attributes by using the simple methods.
llvm-svn: 190499
2013-09-11 08:35:09 +00:00
Matt Arsenault d3471e9ea8 Use type form of getIntPtrType
This doesn't change anything since malloc always returns
address space 0.

llvm-svn: 190498
2013-09-11 07:29:40 +00:00
Matt Arsenault 009faed1be Teach loop-idiom about address space pointer sizes
llvm-svn: 190491
2013-09-11 05:09:42 +00:00
Matt Arsenault 5df49bd703 Add braces
llvm-svn: 190490
2013-09-11 05:09:35 +00:00
Rui Ueyama 106ededc4e Re-submit r190469: YAMLIO: Fix string quoting logic.
llvm-svn: 190485
2013-09-11 04:00:08 +00:00
Hans Wennborg 33ae7cea9f Revert "YAMLIO: Fix string quoting logic." (r190469)
It was turning the buildbots red.

llvm-svn: 190480
2013-09-11 01:59:32 +00:00
Rui Ueyama 38dfffa891 Remove trailing whitespace
llvm-svn: 190472
2013-09-11 00:53:07 +00:00
Rui Ueyama 9a40ae8935 YAMLIO: Fix string quoting logic.
YAMLIO printed a string as is without quotes unless it contains a newline
character. That did not suffice. We also need to quote a string if it starts
with a backquote, quote, double quote or atsign, or it's the empty string.

llvm-svn: 190469
2013-09-11 00:45:48 +00:00
Eli Friedman 8f06d55697 Rename variables for consistency.
No functional change.

llvm-svn: 190466
2013-09-11 00:41:02 +00:00
Eli Friedman 77d7fbb924 Get rid of unused isPodLike definitions.
llvm-svn: 190461
2013-09-11 00:36:54 +00:00
Nico Rieck 92d649ad61 Support ANSI escape code on Windows
In some cases (e.g. when a build system pipes stderr) the Windows console
API cannot be used to color output. For these, provide a way to switch to
ANSI escape codes. This is required for Clang's -fansi-escape-codes option.

llvm-svn: 190460
2013-09-11 00:36:48 +00:00
Eli Friedman 05906faa4d Don't assert on invalid loop vectorization hint.
llvm-svn: 190450
2013-09-10 23:45:25 +00:00
Eli Friedman 3e7dca6718 Fix another mistake in r190442.
Sorry about that; I'll try to be more careful about DEBUG mode.

llvm-svn: 190449
2013-09-10 23:22:56 +00:00
Eli Friedman 78bffa5767 Fix unused variables.
llvm-svn: 190448
2013-09-10 23:18:14 +00:00
Eli Friedman c1f1f852d7 Fix mistake in r190442.
llvm-svn: 190446
2013-09-10 23:09:24 +00:00
Eli Friedman 1891f69323 Remove unused functions.
llvm-svn: 190442
2013-09-10 22:42:31 +00:00
Eric Christopher 13b99d2aba Hoist section call out of loop.
llvm-svn: 190440
2013-09-10 21:49:37 +00:00
Matt Arsenault a90a18e0ea Teach ScalarEvolution about pointer address spaces
llvm-svn: 190425
2013-09-10 19:55:24 +00:00
Matt Arsenault 305a22555a Fix typo
llvm-svn: 190424
2013-09-10 19:54:54 +00:00
Rui Ueyama 471d0c57e7 Add getenv() wrapper that works on multibyte environment variable.
On Windows, character encoding of multibyte environment variable varies
depending on settings. The only reliable way to handle it I think is to use
GetEnvironmentVariableW().

GetEnvironmentVariableW() works on wchar_t string, which is on Windows UTF16
string. That's not ideal because we use UTF-8 as the internal encoding in LLVM.
This patch defines a wrapper function which takes and returns UTF-8 string for
GetEnvironmentVariableW().

The wrapper function does not do any conversion and just forwards the argument
to getenv() on Unix.

Differential Revision: http://llvm-reviews.chandlerc.com/D1612

llvm-svn: 190423
2013-09-10 19:45:51 +00:00
Benjamin Kramer 934f6f39f4 LoopVectorize: PHI nodes are always at the beginning of a block, no need to scan the whole block.
llvm-svn: 190422
2013-09-10 18:46:15 +00:00
Manman Ren 2312ed35d2 Debug Info: create scope children DIEs when the scope DIE is not null.
We try to create the scope children DIEs after we create the scope DIE. But
to avoid emitting empty lexical block DIE, we first check whether a scope
DIE is going to be null, then create the scope children if it is not null.
From the number of children, we decide whether to actually create the scope DIE.

This patch also removes an early exit which checks for a special condition.
It also removes deletion of un-used children DIEs that are generated
because we used to generate children DIEs before the scope DIE.

Deletion of un-used children DIEs may cause problem because we sometimes keep
created DIEs in a member variable of a CU.

llvm-svn: 190421
2013-09-10 18:40:41 +00:00
Manman Ren 34b3dcc3b5 Debug Info: define a DIRef template.
Specialize the constructors for DIRef<DIScope> and DIRef<DIType> to make sure
the Value is indeed a scope ref and a type ref.

Use DIScopeRef for DIScope::getContext and DIType::getContext and use DITypeRef
for getContainingType and getClassType.

DIScope::generateRef now returns a DIScopeRef instead of a "Value *" for
readability and type safety.

llvm-svn: 190418
2013-09-10 18:30:07 +00:00
Jim Grosbach 19ae779af1 ARM: Use the PICADD opcode calculated.
We were figuring out whether to use tPICADD or PICADD, then just using
tPICADD unconditionally anyway. Oops.

A testcase from someone familiar enough with ELF to produce one would
be appreciated. The existing PIC testcase correctly verifies the .s
generated, but that doesn't catch this bug, which only showed up in
direct-to-object mode.

http://llvm.org/bugs/show_bug.cgi?id=17180

llvm-svn: 190417
2013-09-10 17:21:39 +00:00
Logan Chien d532cb6bed Remove unused private member in ARMAsmPrinter.cpp.
This commit removes the unused "AttributeItem" from
ObjectAttributeEmitter.

llvm-svn: 190412
2013-09-10 15:10:02 +00:00
Kostya Serebryany 6805de5467 [asan] refactor the use-after-return API so that the size class is computed at compile time instead of at run-time. llvm part
llvm-svn: 190407
2013-09-10 13:16:56 +00:00
Richard Sandiford 0e0498b288 [SystemZ] Update README.
llvm-svn: 190404
2013-09-10 12:22:45 +00:00
Richard Sandiford a9eb9972e4 [SystemZ] Add TM and TMY
The main complication here is that TM and TMY (the memory forms) set
CC differently from the register forms.  When the tested bits contain
some 0s and some 1s, the register forms set CC to 1 or 2 based on the
value the uppermost bit.  The memory forms instead set CC to 1
regardless of the uppermost bit.

Until now, I've tried to make it so that a branch never tests for an
impossible CC value.  E.g. NR only sets CC to 0 or 1, so branches on the
result will only test for 0 or 1.  Originally I'd tried to do the same
thing for TM and TMY by using custom matching code in ISelDAGToDAG.
That ended up being very ugly though, and would have meant duplicating
some of the chain checks that the common isel code does.

I've therefore gone for the simpler alternative of adding an extra
operand to the TM DAG opcode to say whether a memory form would be OK.
This means that the inverse of a "TM;JE" is "TM;JNE" rather than the
more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE".
I suppose that's arguably less confusing though...

llvm-svn: 190400
2013-09-10 10:20:32 +00:00
Daniel Sanders f561730af8 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190398
2013-09-10 09:51:43 +00:00
Vladimir Medic 65cd57445e Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
llvm-svn: 190397
2013-09-10 09:50:01 +00:00
Vladimir Medic 8826970632 Remove obsolete code from MipsAsmParser.cpp.
llvm-svn: 190396
2013-09-10 09:39:55 +00:00
NAKAMURA Takumi 0229e3557e MCObjectFileInfo.cpp: Fix a couple of possible typo(s), s/DwarfPub/DwarfGnuPub/, in r190344.
XFAIL can be removed. (in r190374)

llvm-svn: 190386
2013-09-10 06:01:56 +00:00
Matt Arsenault d232222f34 Don't use getSetCCResultType for creating a vselect
The vselect mask isn't a setcc.

This breaks in the case when the result of getSetCCResultType
is larger than the vector operands

e.g. %tmp = select i1 %cmp <2 x i8> %a, <2 x i8> %b
when getSetCCResultType returns <2 x i32>, the assertion
that the (MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits())
is hit.

No test since I don't think I can hit this with any of the current
targets. The R600/SI implementation would break, since it returns a
vector of i1 for this, but it doesn't reach ExpandSELECT for other
reasons.

llvm-svn: 190376
2013-09-10 00:41:56 +00:00
Matt Arsenault f631f8c640 Use StringRef::npos for StringRef instead of std::string one
llvm-svn: 190375
2013-09-10 00:41:53 +00:00
Bill Wendling f27e331510 Revert r190366. It was breaking build bots.
llvm-svn: 190373
2013-09-10 00:20:27 +00:00
Andrew Trick 6c88b35090 Enable -misched-cyclicpath by default.
llvm-svn: 190367
2013-09-09 23:31:14 +00:00
Bill Wendling b07305fcd4 Use a default value for the prologue's debug location.
llvm-svn: 190366
2013-09-09 23:28:15 +00:00
Manman Ren 15b2abf229 Debug Info: In DIBuilder, the context fields of a TAG_inheritance and a
TAG_friend are updated to use scope reference.

Added testing cases to verify that class with inheritance can be uniqued.

llvm-svn: 190364
2013-09-09 23:07:58 +00:00
Manman Ren de897a369a Debug Info: move DIScope::getContext back from DwarfDebug.
This partially reverts r190330. DIScope::getContext now returns DIScopeRef
instead of DIScope. We construct a DIScopeRef from DIScope when we are
dealing with subprogram, lexical block or name space.

llvm-svn: 190362
2013-09-09 22:35:23 +00:00
Andrew Trick e1f7bf2c02 mi-sched: smooth out the cyclicpath heuristic.
Arnold's idea.

I generally try to avoid stateful heuristics because it can make
debugging harder. However, we need a way to prevent the latency
priority from dominating, and it somewhat makes sense to schedule
aggressively for latency only within an issue group.

Swift in particular likes this, and it doesn't hurt anyone else:
| Benchmarks/MiBench/consumer-lame              |  10.39% |
| Benchmarks/Misc/himenobmtxpa                  |   9.63% |

llvm-svn: 190360
2013-09-09 22:28:08 +00:00
Jack Carter 170a5f2983 white spaces and long lines
llvm-svn: 190358
2013-09-09 22:02:08 +00:00
Eli Friedman 33d3700716 Don't shrink atomic ops to bool in GlobalOpt.
LLVM IR doesn't currently allow atomic bool load/store operations, and the
transformation is dubious anyway because it isn't profitable on all platforms.

PR17163.

llvm-svn: 190357
2013-09-09 22:00:13 +00:00
Bill Wendling 544d1613fb Set the encoding to '0' if we don't have an MAB.
llvm-svn: 190354
2013-09-09 21:22:44 +00:00
Quentin Colombet 5ab555532b [InstCombiner] Expose opportunities to merge subtract and comparison.
Several architectures use the same instruction to perform both a comparison and
a subtract. The instruction selection framework does not allow to consider
different basic blocks to expose such fusion opportunities.

Therefore, these instructions are “merged” by CSE at MI IR level.

To increase the likelihood of CSE to apply in such situation, we reorder the
operands of the comparison, when they have the same complexity, so that they
matches the order of the most frequent subtract.
E.g.,

icmp A, B
...
sub B, A

<rdar://problem/14514580>

llvm-svn: 190352
2013-09-09 20:56:48 +00:00
Eric Christopher ba506db498 Always add global names. We're adding them in the rest of the code
as well as types.

No functional change as they're not emitted unless the option
is true anyhow.

llvm-svn: 190346
2013-09-09 20:03:20 +00:00
Eric Christopher 5f93bb9299 Rename for consistency.
llvm-svn: 190345
2013-09-09 20:03:17 +00:00
Eric Christopher b0e769411d Add the gnu pubnames and pubtypes sections to the mc object file
handling.

llvm-svn: 190344
2013-09-09 20:03:14 +00:00
Eric Christopher add00faa96 Add constant defines for gnu pubnames and gnu pubtypes - they're used
for the gdb index as the names convey.

llvm-svn: 190343
2013-09-09 20:03:11 +00:00
Bill Wendling 550c76dbd6 Call generateCompactUnwindEncodings() right before we need to output the frame information.
There are more than one paths to where the frame information is emitted. Place
the call to generateCompactUnwindEncodings() into the method which outputs the
frame information, thus ensuring that the encoding is there for every path. This
involved threading the MCAsmBackend object through to this method.

<rdar://problem/13623355>

llvm-svn: 190335
2013-09-09 19:48:37 +00:00
Manman Ren 116868eadd Debug Info: Use DIScopeRef for DIType::getContext.
In DIBuilder, the context field of a TAG_member is updated to use the
scope reference. Verifier is updated accordingly.
    
DebugInfoFinder now needs to generate a type identifier map to have
access to the actual scope. Same applies for BreakpointPrinter.
    
processModule of DebugInfoFinder is called during initialization phase
of the verifier to make sure the type identifier map is constructed early
enough.
    
We are now able to unique a simple class as demonstrated by the added
testing case.

llvm-svn: 190334
2013-09-09 19:47:11 +00:00
Manman Ren 33796c5e98 Debug Info: move DIScope::getContext to DwarfDebug.
DIScope::getContext is a wrapper function that calls the specific getContext
method on each subclass. When we switch DIType::getContext to return DIScopeRef
instead of DIScope, DIScope::getContext can no longer return a DIScope without
a type identifier map.
    
DIScope::getContext is only used by DwarfDebug, so we move it to DwarfDebug
to have easy access to the type identifier map.

llvm-svn: 190330
2013-09-09 19:23:58 +00:00
Bob Wilson e407736a06 Revert patches to add case-range support for PR1255.
The work on this project was left in an unfinished and inconsistent state.
Hopefully someone will eventually get a chance to implement this feature, but
in the meantime, it is better to put things back the way the were.  I have
left support in the bitcode reader to handle the case-range bitcode format,
so that we do not lose bitcode compatibility with the llvm 3.3 release.

This reverts the following commits: 155464, 156374, 156377, 156613, 156704,
156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575,
157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884,
157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100,
159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659,
159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736

llvm-svn: 190328
2013-09-09 19:14:35 +00:00
Manman Ren 3eb9dffc89 Debug Info: Move isSubprogramContext from DebugInfo to DwarfDebug.
This helper function needs the type identifier map when we switch
DIType::getContext to return DIScopeRef instead of DIScope.

Since isSubprogramContext is used by DwarfDebug only, We move it to DwarfDebug
to have easy access to the map.

llvm-svn: 190325
2013-09-09 19:05:21 +00:00
Manman Ren 856191b0d1 Debug Info: Rename DITypeRef to DIScopeRef.
A reference to a scope is more general than a reference to a type since
DIType is a subclass of DIScope.

A reference to a type can be either an identifier for the type or
the DIType itself, while a reference to a scope can be either an
identifier for the type (when the scope is indeed a type) or the
DIScope itself. A reference to a type and a reference to a scope
will be resolved in the same way. The only difference is in the
verifier when a field is a reference to a type (i.e. the containing
type field of a DICompositeType) or a field is a reference to a scope
(i.e. the context field of a DIType).

This is to get ready for switching DIType::getContext to return
DIScopeRef instead of DIScope.

Tighten up isTypeRef and isScopeRef to make sure the identifier is not
empty and the MDNode is DIType for TypeRef and DIScope for ScopeRef.

llvm-svn: 190322
2013-09-09 19:03:51 +00:00
Manman Ren 473c198863 Debug Info: Update isScope to make sure DIType is a scope and
TAG_file_type is also a scope.

llvm-svn: 190321
2013-09-09 19:00:55 +00:00
Akira Hatanaka 9cf069f60a [mips] When double precision loads and stores are split into two i32 loads and
stores, make sure the load or store that accesses the higher half does not have
an alignment that is larger than the offset from the original address.

llvm-svn: 190318
2013-09-09 17:59:32 +00:00
Benjamin Kramer d93817ffe0 [stackprotector] Modernize code with IRBuilder
llvm-svn: 190317
2013-09-09 17:38:01 +00:00
Joey Gouly a5153cb025 [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.
IT blocks can only be one instruction lonf, and can only contain a subset of
the 16 instructions.

Patch by Artyom Skrobov!

llvm-svn: 190309
2013-09-09 14:21:49 +00:00
Aaron Ballman 83d81784df A better way to silence the warning in MSVC (replaces r190304).
llvm-svn: 190308
2013-09-09 14:17:30 +00:00
Aaron Ballman c4280dd977 Silencing a warning about control flow reaching the end of a non-void function.
llvm-svn: 190304
2013-09-09 13:22:45 +00:00
Robert Lytton 3d3194bf06 XCore handling of thread local lowering
Fix XCoreLowerThreadLocal trying to initialise globals
which have no initializer.

Add handling of const expressions containing thread local variables.
These need to be replaced with instructions, as the thread ID is
used to access the thread local variable.

llvm-svn: 190300
2013-09-09 10:42:11 +00:00
Robert Lytton 4809ea41e6 XCore target: change to Sched::Source
This sidesteps a bug in PrescheduleNodesWithMultipleUses() which
does not check if callResources will be affected by the transformation.

llvm-svn: 190299
2013-09-09 10:42:05 +00:00
Robert Lytton e453888379 XCore target: fix weak linkage attribute handling
llvm-svn: 190298
2013-09-09 10:41:57 +00:00
Bill Wendling 58e2d3d856 Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.

Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.

<rdar://problem/13623355>

llvm-svn: 190290
2013-09-09 02:37:14 +00:00
Jiangning Liu 2878dc8fe7 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190288
2013-09-09 02:20:27 +00:00
Manman Ren b09878728f Revert r190269 to fix dragonegg failures.
llvm-svn: 190271
2013-09-08 06:02:56 +00:00
Manman Ren 8ddddadb0b Debug Info: use null instead of "i32 0" in DIBuilder.
For context field of subroutine_type and when creating artificial types.

llvm-svn: 190270
2013-09-08 06:00:42 +00:00
Manman Ren 93da987ea4 Debug Info: pass in DIScope instead of DIDescriptor in createMemberType.
Improve readability. No functionality change.

llvm-svn: 190269
2013-09-08 04:07:59 +00:00
Craig Topper adbb9a121f Add neverHasSideEffects=1 on a couple move instructions.
llvm-svn: 190259
2013-09-08 00:50:45 +00:00
Craig Topper 0a63e1da92 Using popcount should check the popcount feature flag not the SSE41 feature flag.
llvm-svn: 190258
2013-09-08 00:47:31 +00:00
Akira Hatanaka 6379121694 [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.

llvm-svn: 190235
2013-09-07 00:52:30 +00:00
Akira Hatanaka 92ec3bd50b [mips] Place parentheses around && to silence warning.
llvm-svn: 190234
2013-09-07 00:26:26 +00:00
Richard Smith d9e5ff24e6 Remove verifier check that attribute 'builtin' is only applied to calls to
functions marked 'nobuiltin'. That approach doesn't play well with LTO, and
there's no harm in marking a call as 'builtin' if it was going to be a builtin
regardless.

llvm-svn: 190233
2013-09-07 00:25:48 +00:00
Akira Hatanaka 6a3fe57444 [mips] Add definition of instruction "drotr32" (double rotate right plus 32).
llvm-svn: 190232
2013-09-07 00:18:01 +00:00
Manman Ren c4ae9b3aeb Debug Info: Use identifier to reference DIType in containing type field of
a DISubprogram.
    
Verifier is updated accordingly.

llvm-svn: 190229
2013-09-07 00:04:05 +00:00
Akira Hatanaka 3121353c99 [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.

llvm-svn: 190226
2013-09-07 00:02:02 +00:00
Manman Ren 275520608b Debug Info: pass in VTableHolder as DIType instead of MDNode *.
Remove one cast and improve readability. No functionality change.

llvm-svn: 190225
2013-09-06 23:54:23 +00:00
Akira Hatanaka 79e38cde37 [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
llvm-svn: 190224
2013-09-06 23:52:46 +00:00
Akira Hatanaka 50eebac68b [mips] Delete unused classes and defs.
llvm-svn: 190221
2013-09-06 23:42:58 +00:00
Akira Hatanaka 2c544d8ed5 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220
2013-09-06 23:40:15 +00:00
Akira Hatanaka dffc542123 [mips] Set instruction itineraries of loads, stores and conditional moves.
llvm-svn: 190219
2013-09-06 23:28:24 +00:00
Manman Ren d8c68b1852 TBAA: add isTBAAVtableAccess to MDNode so clients can call the function
instead of having its own implementation.

The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp
since it is related to the format of TBAA metadata.

The path for struct-path tbaa will be exercised by
test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and
vptr_update.ll when struct-path tbaa is on by default.

llvm-svn: 190216
2013-09-06 22:47:05 +00:00
Aaron Watry 372cecf642 R600: Add support for LDS atomic subtract
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190200
2013-09-06 20:17:42 +00:00
Manman Ren d8f798ea97 Debug Info: Use identifier to reference DIType in containing type field of
a DICompositeType.
    
Verifier is updated accordingly.

llvm-svn: 190190
2013-09-06 18:46:00 +00:00
Manman Ren 277206fa28 Debug Info: Move a helper function getTypeIdentifier from DIBuilder to be part
of DIType.
    
Implement DIType::generateRef to return a type reference. This function will be
used in setContaintingType and in DIBuilder to generete the type reference.
    
No functionality change.

llvm-svn: 190188
2013-09-06 18:27:00 +00:00
Andrew Trick b248b4a1de mi-sched: cleanup register pressure update, remove a FIXME.
llvm-svn: 190181
2013-09-06 17:32:47 +00:00
Andrew Trick c573cd905a mi-sched: improve regpressure tracing.
llvm-svn: 190180
2013-09-06 17:32:44 +00:00
Andrew Trick 7609b7d1b5 mi-sched: print tree size in -view-misched-dags
llvm-svn: 190179
2013-09-06 17:32:42 +00:00
Andrew Trick ffdbefb90c mi-sched: register pressure update tracing.
llvm-svn: 190178
2013-09-06 17:32:39 +00:00
Andrew Trick ddffae9027 mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.
The latency based scheduling could induce spills in some cases.

llvm-svn: 190177
2013-09-06 17:32:36 +00:00
Andrew Trick 75e411cc8e Added MachineSchedPolicy.
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.

llvm-svn: 190176
2013-09-06 17:32:34 +00:00
Matthias Braun 305ef7f5b0 avoid unnecessary direct access to LiveInterval::ranges
llvm-svn: 190170
2013-09-06 16:44:32 +00:00
Matthias Braun 90e0d3c03a remove unused argument from LiveRanges::join()
llvm-svn: 190169
2013-09-06 16:44:29 +00:00
Matthias Braun c0ad7bfa62 remove pointless assert
The if above it ensures the property anyway.

llvm-svn: 190168
2013-09-06 16:44:27 +00:00
Matthias Braun b348d9703c fix comment
There's no 'B3' in the example.

llvm-svn: 190167
2013-09-06 16:44:25 +00:00
Daniel Sanders af7f805b96 [mips][msa] Indentation
llvm-svn: 190156
2013-09-06 13:25:06 +00:00
Daniel Sanders 636f72fc08 [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155
2013-09-06 13:15:05 +00:00
Vladimir Medic b936da159e This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
llvm-svn: 190154
2013-09-06 13:08:00 +00:00
Daniel Sanders 563e5eabe5 [mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153
2013-09-06 13:01:47 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Daniel Sanders 41fb2c0d0e [mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151
2013-09-06 12:50:52 +00:00
Daniel Sanders fa1b0fa77e [mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150
2013-09-06 12:44:13 +00:00
Vladimir Medic e0fbb44a48 This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Tim Northover 950fcc0577 SelectionDAG: create correct BooleanContent constants
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

llvm-svn: 190147
2013-09-06 12:38:12 +00:00
Daniel Sanders d719f5281c [mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146
2013-09-06 12:32:57 +00:00
Daniel Sanders b2b7c0a044 [mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145
2013-09-06 12:30:43 +00:00
Vladimir Medic dde3d582a2 This patch adds support for microMIPS disassembler and disassembler make check tests.
llvm-svn: 190144
2013-09-06 12:30:36 +00:00
Daniel Sanders 2322f5d090 [mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143
2013-09-06 12:28:13 +00:00
Daniel Sanders 9148218cbe [mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190142
2013-09-06 12:25:47 +00:00
Daniel Sanders 92c40a5796 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190141
2013-09-06 12:23:19 +00:00
Daniel Sanders 13d5e2f376 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190140
2013-09-06 12:10:24 +00:00
Richard Sandiford 5bc670bb55 [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.

llvm-svn: 190138
2013-09-06 11:51:39 +00:00
Daniel Sanders 63b97d5ae5 [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change

llvm-svn: 190134
2013-09-06 11:01:38 +00:00
Daniel Sanders 02a3007608 [mips][msa] Made the operand register sets optional for the 3R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190133
2013-09-06 10:59:24 +00:00
Daniel Sanders db12ab7b7c [mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
No functional change

llvm-svn: 190131
2013-09-06 10:55:15 +00:00
Richard Sandiford 4943bc393a [SystemZ] Use XC for a memset of 0
llvm-svn: 190130
2013-09-06 10:25:07 +00:00
Matt Arsenault 8227b9f69c Use type helper functions.
llvm-svn: 190113
2013-09-06 00:37:24 +00:00
Matt Arsenault 37d42ecaff Teach CodeGenPrepare about address spaces
llvm-svn: 190112
2013-09-06 00:18:43 +00:00
Tom Stellard 8bc633ac09 R600: Coding style
llvm-svn: 190110
2013-09-05 23:55:13 +00:00
Juergen Ributzka 53d0b492f5 [X86] Perform VSELECT DAG combines also before DAG type legalization.
If the DAG already has only legal types, then the second round of DAG combines
is skipped. In this case VSELECT+SETCC patterns that match a more efficient
instruction (e.g. min/max) are never recognized.

This fix allows VSELECT+SETCC combines if the types are already legal before DAG
type legalization.

Reviewer: Nadav
llvm-svn: 190105
2013-09-05 23:02:56 +00:00
Kevin Enderby 09cdb4385f Fixed a crash in the integrated assembler for Mach-O when a symbol difference
expression uses an assembler temporary symbol from an assignment.  In this case
the symbol does not have a fragment so the use of getFragment() would be NULL
and caused a crash. In the case of an assembler temporary symbol we want to use
the AliasedSymbol (if any) which will create a local relocation entry, but if
it is not an assembler temporary symbol then let it use that symbol with an
external relocation entry.

rdar://9356266

llvm-svn: 190096
2013-09-05 20:25:06 +00:00
Matt Arsenault e6db76071c Consistently use dbgs() in debug printing
llvm-svn: 190093
2013-09-05 19:48:28 +00:00
Matt Arsenault 6f24379974 R600: Fix i64 to i32 trunc on SI
llvm-svn: 190091
2013-09-05 19:41:10 +00:00
Rafael Espindola d21ac19bda Remove unused argument.
llvm-svn: 190090
2013-09-05 19:15:21 +00:00
Yunzhong Gao 8c0f5067cc Improve handling of .file, .include and .incbin directives to
allow escaped octal character sequences.

The patch was discussed in Phabricator. See:
http://llvm-reviews.chandlerc.com/D1289

llvm-svn: 190089
2013-09-05 19:14:26 +00:00
Manman Ren 60352032bf Debug Info: Use identifier to reference DIType in base type field of
ptr_to_member.

We introduce a new class DITypeRef that represents a reference to a DIType.
It wraps around a Value*, which can be either an identifier in MDString
or an actual MDNode. The class has a helper function "resolve" that
finds the actual MDNode for a given DITypeRef.

We specialize getFieldAs to return a field that is a reference to a
DIType. To correctly access the base type field of ptr_to_member,
getClassType now calls getFieldAs<DITypeRef> to return a DITypeRef.

Also add a typedef for DITypeIdentifierMap and a helper
generateDITypeIdentifierMap in DebugInfo.h. In DwarfDebug.cpp, we keep
a DITypeIdentifierMap and call generateDITypeIdentifierMap to actually
populate the map.

Verifier is updated accordingly.

llvm-svn: 190081
2013-09-05 18:48:31 +00:00
Tom Stellard 13c68ef88b R600: Add support for local memory atomic add
llvm-svn: 190080
2013-09-05 18:38:09 +00:00
Tom Stellard 53f2f90eb4 R600: Expand SELECT nodes rather than custom lowering them
llvm-svn: 190079
2013-09-05 18:38:03 +00:00
Tom Stellard de60e25278 R600: Fix incorrect LDS size calculation
GlobalAdderss nodes that appeared in more than one basic block were
being counted twice.

llvm-svn: 190078
2013-09-05 18:37:57 +00:00
Tom Stellard d50bb3c8d4 R600/SI: Don't emit S_WQM_B64 instruction for compute shaders
llvm-svn: 190077
2013-09-05 18:37:52 +00:00
Tom Stellard 624741fded R600: Fix segfault in R600TextureIntrinsicReplacer
This pass was segfaulting when it ran into a non-intrinsic function
call.  Function calls are not supported, so now instead of segfaulting,
we will get an assertion failure with a nice error message.

I'm not sure how to test this using lit.

llvm-svn: 190076
2013-09-05 18:37:45 +00:00
Eric Christopher cf7289f6d9 Move accelerator table defines and constants to Dwarf.h since
we're proposing it for DWARF5.

No functional change intended.

llvm-svn: 190074
2013-09-05 18:20:16 +00:00
Eric Christopher b4e2cc49ef Reformat.
llvm-svn: 190064
2013-09-05 16:46:43 +00:00
Joey Gouly 926d3f5809 [ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.

llvm-svn: 190055
2013-09-05 15:35:24 +00:00
Richard Barton 8d519fe015 Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.

The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.

HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.

Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.

llvm-svn: 190053
2013-09-05 14:14:19 +00:00
Tilmann Scheller 841a9ccfed Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.

llvm-svn: 190047
2013-09-05 11:59:43 +00:00
Tilmann Scheller a1787a5835 ARM: Add GPR register class excluding LR for use with the ADR instruction.
This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.

Patch by Daniel Stewart!
   

llvm-svn: 190043
2013-09-05 11:10:31 +00:00
Richard Sandiford 178273a174 [SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which
all operands are memory.

llvm-svn: 190041
2013-09-05 10:36:45 +00:00
Nick Lewycky 2c88067a46 Declare missing dependency on AliasAnalysis. Patch by Liu Xin!
llvm-svn: 190035
2013-09-05 08:19:58 +00:00
Venkatraman Govindaraju 55ecb10e99 [Sparc] Correctly handle call to functions with ReturnsTwice attribute.
In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.

This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.  

llvm-svn: 190033
2013-09-05 05:32:16 +00:00
Bill Wendling 3af441f1af Fix comments to reflect reality.
llvm-svn: 190021
2013-09-05 00:54:52 +00:00
Eric Christopher 4202633ea6 Formatting.
llvm-svn: 190019
2013-09-05 00:22:35 +00:00
Andrew Trick ed20075d19 mi-sched: Force bottom up scheduling for generic targets.
Fast register pressure tracking currently only takes effect during
bottom up scheduling. Forcing this is a bit faster and simpler for
targets that don't have many scheduling constraints and don't need
top-down scheduling.

llvm-svn: 190014
2013-09-04 23:54:00 +00:00
Nick Kledzik fe6813f0e1 Add names for mach-o permissions bits and use the symbol names in place of magic numbers
llvm-svn: 190013
2013-09-04 23:53:44 +00:00
Bill Wendling b1e21831b7 Add missing header line.
llvm-svn: 190004
2013-09-04 22:35:41 +00:00
Bill Wendling 10543925bd Use ArrayRef instead of explicit container.
llvm-svn: 190003
2013-09-04 22:35:29 +00:00
Eric Christopher e31e072c33 Remove hack ensuring that darwin didn't produce dwarf > 3 for modules
without a limiting factor.

Update all testcases accordingly.

llvm-svn: 190002
2013-09-04 22:21:24 +00:00
Eric Christopher c9f1e785d5 Revert "Revert r189902 as the workaround shouldn't be necessary anymore."
Needs testcase updates.

llvm-svn: 190000
2013-09-04 21:36:52 +00:00
Eric Christopher b72ef638f4 Revert r189902 as the workaround shouldn't be necessary anymore.
llvm-svn: 189999
2013-09-04 21:26:56 +00:00
Andrew Trick b05db8e0b9 comment typo
llvm-svn: 189997
2013-09-04 21:12:05 +00:00
Andrew Trick 2a749ee0b9 Remove dead subtree limit code.
llvm-svn: 189995
2013-09-04 21:00:20 +00:00
Andrew Trick 856ecd9ab3 -view-misched-dags, better pruning.
llvm-svn: 189994
2013-09-04 21:00:18 +00:00
Andrew Trick ef54c59490 mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.
llvm-svn: 189993
2013-09-04 21:00:16 +00:00
Andrew Trick 1ab16d9ecf 80 columns
llvm-svn: 189992
2013-09-04 21:00:13 +00:00
Andrew Trick 66c3dfbf8c mi-sched: Suppress register pressure tracking when the scheduling window is too small.
If the instruction window is < NumRegs/2, pressure tracking is not
likely to be effective. The scheduler has to process a very large
number of tiny blocks. We want this to be fast.

llvm-svn: 189991
2013-09-04 21:00:11 +00:00
Andrew Trick a6e877707f mi-sched: Load clustering is a bit to expensive to enable unconditionally.
llvm-svn: 189990
2013-09-04 21:00:08 +00:00
Andrew Trick 8c699c93b2 mi-sched: Reuse an invalid HazardRecognizer to save compile time.
llvm-svn: 189989
2013-09-04 21:00:05 +00:00
Andrew Trick 310190e21f mi-sched: bypass heuristic checks when regpressure tracking is disabled.
llvm-svn: 189988
2013-09-04 21:00:02 +00:00
Andrew Trick b6e74712b6 Added -misched-regpressure option.
Register pressure tracking is half the complexity of the
scheduler. It's useful to be able to turn it off for compile time and
performance comparisons.

llvm-svn: 189987
2013-09-04 20:59:59 +00:00
Rafael Espindola b7c0b4a327 Rename some variables to match the style guide.
I am about to patch this code, and this makes the diff far more readable.

llvm-svn: 189982
2013-09-04 20:08:46 +00:00
Vincent Lejeune 744efa4dca R600: Use shared op optimization when checking cycle compatibility
llvm-svn: 189981
2013-09-04 19:53:54 +00:00
Vincent Lejeune 7e2c83256b R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 189980
2013-09-04 19:53:46 +00:00
Vincent Lejeune 4d5c5e53d0 R600: Use SchedModel enum for is{Trans,Vector}Only functions
llvm-svn: 189979
2013-09-04 19:53:30 +00:00
Eric Christopher 9adc55faa7 Unify and clean up.
llvm-svn: 189977
2013-09-04 19:53:21 +00:00
Jim Grosbach 13654dd303 ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.
These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.

I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).

PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093
llvm-svn: 189972
2013-09-04 19:08:44 +00:00
Rafael Espindola b832d49822 Small simplification given that insert of an empty range is a nop.
llvm-svn: 189971
2013-09-04 18:53:21 +00:00
Rafael Espindola 49a6c153c9 Refactor duplicated logic to a helper function.
No functionality change.

llvm-svn: 189969
2013-09-04 18:37:36 +00:00
Rafael Espindola 9406516af1 Remove dead code.
llvm-svn: 189967
2013-09-04 18:16:02 +00:00
Arnold Schwaighofer d7e8d92606 Swift: Only build vldm/vstm with q register aligned register lists
Unaligned vldm/vstm need more uops and therefore are slower in general on swift.

radar://14522102

llvm-svn: 189961
2013-09-04 17:41:16 +00:00
Silviu Baranga 5cba070ce2 Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact.
llvm-svn: 189958
2013-09-04 17:05:18 +00:00
Rafael Espindola 128c5ea902 Revert "Add r159136 back now that pr13124 has been fixed."
This reverts commit r189886.

I found a corner case where this optimization is not valid:

Say we have a "linkonce_odr unnamed_addr" in two translation units:
* In TU 1 this optimization kicks in and makes it hidden.
* In TU 2 it gets const merged with a constant that is *not* unnamed_addr,
  resulting in a non unnamed_addr constant with default visibility.
* The static linker rules for combining visibility them produce a hidden
  symbol, which is incorrect from the point of view of the non unnamed_addr
  constant.

The one place we can do this is when we know that the symbol is not used from
another TU in the same shared object, i.e., during LTO. I will move it there.

llvm-svn: 189954
2013-09-04 16:09:01 +00:00
Alexander Kornienko 9aa60fd6f8 Move generic isPrint and columnWidth implementations to a separate header/source to allow using both generic and system-dependent versions on win32.
Summary:
This is needed so we can use generic columnWidthUTF8 in clang-format on
win32 simultaneously with a separate system-dependent implementations of
isPrint/columnWidth in TextDiagnostic.cpp to avoid attempts to print Unicode
characters using narrow-character interfaces (which is not supported on Windows,
and we'll have to figure out how to handle this).

Reviewers: jordan_rose

Reviewed By: jordan_rose

CC: llvm-commits, klimek

Differential Revision: http://llvm-reviews.chandlerc.com/D1559

llvm-svn: 189952
2013-09-04 16:00:12 +00:00
Rafael Espindola fac3a018d1 Error on linking appending globals with different unnamed_addr.
llvm-svn: 189950
2013-09-04 15:33:34 +00:00
Venkatraman Govindaraju b803cec00e [Sparc] Fix an assertion failure while lowering fcmp on long double.
This assertion is triggered because an integer constant is created with wrong
  type.

llvm-svn: 189948
2013-09-04 15:15:20 +00:00
Rafael Espindola fd9a9415f5 Fix linking of unnamed_addr in functions.
llvm-svn: 189945
2013-09-04 14:59:03 +00:00
NAKAMURA Takumi 7a0423468e Support/Process: Add comments about PageSize and AllocationGranularity on Cygwin and Win32.
llvm-svn: 189940
2013-09-04 14:12:26 +00:00
NAKAMURA Takumi 65fc51bbe2 MemoryBuffer.cpp: Don't peek the next page if file is multiple of *physical* pagesize(4k) but is not multiple of AllocationGranularity(64k), when a null terminator is required, on cygwin and win32.
For example, r189780's SparcISelLowering.cpp has the size 98304. It crashed clang to touch a null terminator on cygwin.

FIXME: It's not good to hardcode 4096 here. dwPageSize shows 4096.
llvm-svn: 189939
2013-09-04 14:12:19 +00:00
NAKAMURA Takumi 9542678508 Whitespace.
llvm-svn: 189938
2013-09-04 14:12:12 +00:00
Rafael Espindola d4885daefa Fix linking of unnamed_addr.
This was regression from r134829. When linking we have to be conservative. If
one of the symbols has a significant address, then the result should have it
too.

llvm-svn: 189935
2013-09-04 14:05:09 +00:00
Tim Northover dc647a2603 InstCombine: allow unmasked icmps to be combined with logical ops
"(icmp op i8 A, B)" is equivalent to "(icmp op i8 (A & 0xff), B)" as a
degenerate case. Allowing this as a "masked" comparison when analysing "(icmp)
&/| (icmp)" allows us to combine them in more cases.

rdar://problem/7625728

llvm-svn: 189931
2013-09-04 11:57:17 +00:00
Tim Northover c0756c454c InstCombine: look for masked compares with subset relation
Even in cases which aren't universally optimisable like "(A & B) != 0 && (A &
C) != 0", the masks can make one of the comparisons completely redundant. In
this case, since we've gone to the effort of spotting masked comparisons we
should combine them.

rdar://problem/7625728

llvm-svn: 189930
2013-09-04 11:57:13 +00:00
Hao Liu d4aede098f Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189925
2013-09-04 09:28:24 +00:00
Michael Gottesman c89466fc22 Revert "Revert "Remove the darwin gdb option, that version of gdb is now dead and the rest of the compatibility should be done on a dwarf-N level.""
This reverts commit r189913.

Talked with Eric on IRC. I am going to XFAIL the failing test since it
is using what Eric described as "the member hack" which was needed on
that old GDB.

Sorry for the noise!

llvm-svn: 189914
2013-09-04 04:39:38 +00:00
Michael Gottesman a318370b8d Revert "Remove the darwin gdb option, that version of gdb is now dead and the rest of the compatibility should be done on a dwarf-N level."
This reverts commit r189903.

This commit broke the phase 1 buildbot for a while.

http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RAincremental/builds/6684

llvm-svn: 189913
2013-09-04 04:31:56 +00:00
Michael Gottesman c9f5859f81 Add llvm namespace to llvm::next.
llvm-svn: 189912
2013-09-04 04:26:09 +00:00
Michael Gottesman 114ac1a230 Use llvm::next() instead of incrementing begin iterators of std::vector.
Iterator of std::vector may be implemented as a raw pointer. In
this case begin iterators are rvalues and cannot be incremented.
For example, this is the case with STDCXX implementation of vector.

Patch by Konstantin Tokarev <annulen@yandex.ru>.

llvm-svn: 189911
2013-09-04 04:19:01 +00:00
Eric Christopher 614dc83603 Remove the darwin gdb option, that version of gdb is now dead and
the rest of the compatibility should be done on a dwarf-N level.

llvm-svn: 189903
2013-09-04 02:02:10 +00:00
Eric Christopher 38f1c64098 Make the default dwarf version 3 for darwin when we can't find one
in the module. Add a FIXME with a comment about darwin's ld.

llvm-svn: 189902
2013-09-04 01:38:30 +00:00
Rafael Espindola 5eb7df68bf Add r159136 back now that pr13124 has been fixed.
Original message:
If a constant or a function has linkonce_odr linkage and unnamed_addr, mark
hidden. Being linkonce_odr guarantees that it is available in every dso that
needs it. Being a constant/function with unnamed_addr guarantees that the
copies don't have to be merged.

llvm-svn: 189886
2013-09-03 23:34:36 +00:00
Jim Grosbach 6c6b425b30 X86: Mark non-crashing report_fatal_errors() as such.
Previously, the clang crash handling code would kick in and give a crash
report for these, even though they're not that sort of error.

rdar://14882264

llvm-svn: 189878
2013-09-03 23:02:00 +00:00
Michael Gottesman 469a80cb30 [objc-arc] Remove dead code from previous commit.
llvm-svn: 189870
2013-09-03 22:40:56 +00:00
Michael Gottesman e29b1c1825 [objc-arc] Turn off the objc_retainBlock -> objc_retain optimization.
The reason that I am turning off this optimization is that there is an
additional case where a block can escape that has come up. Specifically, this
occurs when a block is used in a scope outside of its current scope.

This can cause a captured retainable object pointer whose life is preserved by
the objc_retainBlock to be deallocated before the block is invoked.

An example of the code needed to trigger the bug is:

----
\#import <Foundation/Foundation.h>
int main(int argc, const char * argv[]) {
  void (^somethingToDoLater)();

  {
    NSObject *obj = [NSObject new];

    somethingToDoLater = ^{
      [obj self]; // Crashes here
    };
  }

  NSLog(@"test.");

  somethingToDoLater();
  return 0;
}
----

In the next commit, I remove all the dead code that results from this.

Once I put in the fixing commit I will bring back the tests that I deleted in
this commit.

rdar://14802782.
rdar://14868830.

llvm-svn: 189869
2013-09-03 22:40:54 +00:00
Eric Christopher 25b7adc8ce Add a hashing routine that handles hashing types. Add a test for
hashing the contents of DW_FORM_data1 on top of a type with attributes.

llvm-svn: 189862
2013-09-03 21:57:57 +00:00
Eric Christopher b86e2ad819 Sentences end with periods.
llvm-svn: 189861
2013-09-03 21:57:50 +00:00
Nadav Rotem 5d78dba6d9 Enable late-vectorization by default.
This patch changes the default setting for the LateVectorization flag that controls where the loop-vectorizer is ran.

Perf gains:
SingleSource/Benchmarks/Shootout/matrix -37.33%
MultiSource/Benchmarks/PAQ8p/paq8p  -22.83%
SingleSource/Benchmarks/Linpack/linpack-pc  -16.22%
SingleSource/Benchmarks/Shootout-C++/ary3 -15.16%
MultiSource/Benchmarks/TSVC/NodeSplitting-flt/NodeSplitting-flt -10.34%
MultiSource/Benchmarks/TSVC/NodeSplitting-dbl/NodeSplitting-dbl -7.12%

Regressions:
SingleSource/Benchmarks/Misc/lowercase  15.10%
MultiSource/Benchmarks/TSVC/Equivalencing-flt/Equivalencing-flt 13.18%
SingleSource/Benchmarks/Shootout-C++/matrix 8.27%
SingleSource/Benchmarks/CoyoteBench/lpbench 7.30%

llvm-svn: 189858
2013-09-03 21:33:17 +00:00
Matt Arsenault 3dfe54e954 Teach InstCombineLoadCast about address spaces.
This is another one that doesn't matter much,
but uses the right GEP index types in the first
place.

llvm-svn: 189854
2013-09-03 21:05:48 +00:00
Matt Arsenault e38e4cdc46 Use type form of getIntPtrType in alloca visitor.
This doesn't actually matter, since alloca is always
0 address space, but this is more consistent.

llvm-svn: 189853
2013-09-03 21:05:15 +00:00
Bill Wendling c656b8e402 WIP: Refactor some code so that it can be called by more than just one method. No functionality change.
llvm-svn: 189849
2013-09-03 20:59:07 +00:00
Jim Grosbach 20c925dbf2 Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""
This reverts commit r189648.

Fixes for the previously failing clang-side arm_neon_intrinsics test
cases will be checked in separately.

llvm-svn: 189841
2013-09-03 20:08:17 +00:00
Eric Christopher e020fa7c9c Add the rest of the stock attributes to the attribute table.
This won't affect the kinds of hashes we test for as we actually
do hashing based on form and attribute. Change the fission-hash
testcase one last time to handle DW_AT_comp_dir.

llvm-svn: 189840
2013-09-03 20:00:20 +00:00
Yi Jiang aeb5b46a85 In this patch we are trying to do two things:
1) If the width of vectorization list candidate is bigger than vector reg width, we will break it down to fit the vector reg.
2) We do not vectorize the width which is not power of two.

The performance result shows it will help some spec benchmarks. mesa improved 6.97% and ammp improved 1.54%. 

llvm-svn: 189830
2013-09-03 17:26:04 +00:00
Richard Sandiford 113c870397 [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL
For now this just handles simple comparisons of an ANDed value with zero.
The CC value provides enough information to do any comparison for a
2-bit mask, and some nonzero comparisons with more populated masks,
but that's all future work.

llvm-svn: 189819
2013-09-03 15:38:35 +00:00
Evgeniy Stepanov e95d37c81d [msan] Fix handling of select with struct arguments.
llvm-svn: 189796
2013-09-03 13:05:29 +00:00
Evgeniy Stepanov 566f591404 [msan] Fix select instrumentation.
Select condition shadow was being ignored resulting in false negatives.
This change OR-s sign-extended condition shadow into the result shadow.

llvm-svn: 189785
2013-09-03 10:04:11 +00:00
Venkatraman Govindaraju 59039dc1bf [Sparc] Add support for soft long double (fp128).
llvm-svn: 189780
2013-09-03 04:11:59 +00:00
Craig Topper 8a1028f75e Add hadSideEffects=0 to some instructions.
llvm-svn: 189779
2013-09-03 03:56:17 +00:00
Venkatraman Govindaraju 01cb19f93c [Sparc] Implement spill and load for long double(f128) registers.
llvm-svn: 189768
2013-09-02 18:32:45 +00:00
Tilmann Scheller 63872ce19f ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.
Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189766
2013-09-02 17:09:01 +00:00
Tilmann Scheller 8f79ee99be Revert 189756 for now, it doesn't match what rdar://14871821 really wants.
What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. 

llvm-svn: 189763
2013-09-02 15:48:17 +00:00
Tilmann Scheller f49c80178e ARM: Default to Swift when compiling for iOS 6 or later.
Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189756
2013-09-02 12:01:58 +00:00
Craig Topper b25f0f5538 Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028.
llvm-svn: 189742
2013-09-02 07:53:17 +00:00
Elena Demikhovsky 402ee64f13 AVX-512: updated the list of high-latency instructions.
llvm-svn: 189740
2013-09-02 07:41:01 +00:00
Elena Demikhovsky 534015e550 AVX-512: gather-scatter tests; added foldable instructions;
Specify GATHER/SCATTER as heavy instructions.

llvm-svn: 189736
2013-09-02 07:12:29 +00:00
Elena Demikhovsky 843657c311 llvm interpreter: select, shuffle and insertelement instructions.
This patch implements vector support for  select instruction and adds specific vector instructions : shuffle and insertelement. (tests are also included)
and functions lle_X_memset, lle_X_memcpy added.

Done by Veselov, Yuri (mailto:Yuri.Veselov@intel.com)

llvm-svn: 189735
2013-09-02 06:40:09 +00:00
Chandler Carruth 14aae04029 Fix some rather confusing indentation and control flow in the errno
printing routine. This is made harder to see due to the surprising
formatting, inconsistent brace usage, and repeated conditions that all
test the same thing.

The only "consequence" of this bug is re-assigning 'str' to an empty
string when computing the error string for an error number of 0 in the
event of a non-GNU strerror_r routine. So, nothing to see here other
than cleanup. It did help me find PR17055 in clang-format though.

llvm-svn: 189734
2013-09-02 05:55:10 +00:00
Elena Demikhovsky 4def4b088f AVX-512: Added GATHER and SCATTER instructions.
llvm-svn: 189729
2013-09-01 14:24:41 +00:00
Charles Davis 8bdfafd505 Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
llvm-svn: 189728
2013-09-01 04:28:48 +00:00
Reed Kotler 5fdadcef7a Make sure we don't generate stubs for any of these functions because they
don't exist in libc. This is really not the right way to solve this problem;
but it's not clear to me at this time exactly what is the right way.
If we create stubs here, they will cause link errors because these functions
do not exist in libc.

llvm-svn: 189727
2013-09-01 04:12:59 +00:00
Benjamin Kramer bda73fff49 Mark an unreachable code path with llvm_unreachable. Pacifies GCC.
llvm-svn: 189726
2013-08-31 21:20:04 +00:00
Benjamin Kramer 2702caad08 SimplifyLibCalls: When emitting an overloaded fp function check that it's available.
The existing code missed some edge cases when e.g. we're going to emit sqrtf but
only the availability of sqrt was checked. This happens on odd platforms like
windows.

llvm-svn: 189724
2013-08-31 18:19:35 +00:00
Andrew Trick 2c4f8b7ee8 Fix my previous checkin to updatePressureDiffs.
There was one case that we could hit a DebugValue where I didn't think
to check. DebugValues are evil. No checkinable test case, sorry. It's
an obvious fix.

llvm-svn: 189717
2013-08-31 05:17:58 +00:00
Bill Schmidt eb8d6f7da0 [PowerPC] Fast-isel cleanup patch.
Here are a few miscellaneous things to tidy up the PPC64 fast-isel
implementation.  I corrected a couple of commentary lapses, and added
documentation of future opportunities.  I also implemented
TargetMaterializeAlloca, which I somehow forgot when I split up the
original huge patch.

Finally, I decided to delete SelectCmp.  I hadn't previously hooked it
in to TargetSelectInstruction(), and when I did I realized it wasn't
serving any useful purpose.  This is only useful for compares that
don't feed a branch in the same block, and to handle that we would
have to have logic to interpret i1 as a condition register.  This
could probably be done, but would require Unseemly Hackery, and
honestly does not seem worth the hassle.

This ends the current patch series.

llvm-svn: 189715
2013-08-31 02:33:40 +00:00
Bill Schmidt 9d9510d806 [PowerPC] Add integer truncation support to fast-isel.
This is the last substantive patch I'm planning for fast-isel in the
near future, adding fast selection of integer truncates.  There are
certainly more things that can be improved (many of which are called
out in FIXMEs), but for now we are catching most of the important
cases.

I'll document some of the remaining work in a cleanup patch shortly.

llvm-svn: 189706
2013-08-30 23:31:33 +00:00
Bill Schmidt 0954ea1b5e Correct partially defined variable
llvm-svn: 189705
2013-08-30 23:25:30 +00:00
Bill Schmidt 8470b0f96c [PowerPC] Call support for fast-isel.
This patch adds fast-isel support for calls (but not intrinsic calls
or varargs calls).  It also removes a badly-formed assert.  There are
some new tests just for calls, and also for folding loads into
arguments on calls to avoid extra extends.

llvm-svn: 189701
2013-08-30 22:18:55 +00:00
Richard Mitton 79917a913e Build fix
llvm-svn: 189699
2013-08-30 21:32:42 +00:00
Richard Mitton 576ee003d0 Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.
llvm-svn: 189698
2013-08-30 21:19:48 +00:00
Bill Wendling 2865be79f8 Compulsive reformatting.
llvm-svn: 189697
2013-08-30 21:07:33 +00:00
Daniel Dunbar eb6c708d92 [conf] Add config variable to disable crash related overrides.
- We do some nasty things w.r.t. installing or overriding signal handlers in
   order to improve our crash recovery support or interaction with crash
   reporting software, and those things are not necessarily appropriate when
   LLVM is being linked into a client application that has its own ideas about
   how to do things. This gives those clients a way to disable that handling at
   build time.

 - Currently, the code this guards is all Apple specific, but other platforms
   might have the same concerns so I went for a more generic configure
   name. Someone who is more familiar with library embedding on Windows can
   handle choosing which of the Windows/Signals.inc behaviors might make sense
   to go under this flag.

 - This also fixes the proper autoconf'ing of ENABLE_BACKTRACES. The code
   expects it to be undefined when disabled, but the autoconf check was just
   defining it to 0.

llvm-svn: 189694
2013-08-30 20:39:21 +00:00