Commit Graph

141 Commits

Author SHA1 Message Date
Owen Anderson 454e1c7abb Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
Jim Grosbach 06210a28de 80 columns.
llvm-svn: 135047
2011-07-13 17:25:55 +00:00
Jim Grosbach 4def704a21 Pseudo-ize t2MOVCC[ri].
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.

llvm-svn: 134242
2011-07-01 17:14:11 +00:00
Jim Grosbach e4750ef6ec Pseudo-ize the Thumb tTPsoft instruction.
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.

llvm-svn: 134178
2011-06-30 19:38:01 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Chris Lattner 1d0c25756e use the MachineInstrBuilder operator-> to simplify some code.
There are probably more instances of this floating around.

llvm-svn: 130474
2011-04-29 05:24:29 +00:00
Evan Cheng 4079133796 Do not lose mem_operands while lowering VLD / VST intrinsics.
llvm-svn: 129738
2011-04-19 00:04:03 +00:00
Owen Anderson 77aa266de8 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
llvm-svn: 128940
2011-04-05 21:48:57 +00:00
Owen Anderson f7678b83d2 Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
llvm-svn: 128892
2011-04-05 17:24:25 +00:00
Owen Anderson d6c5a741b5 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
llvm-svn: 128461
2011-03-29 16:45:53 +00:00
Owen Anderson 38aa83fa24 There are two pseudos in this case that are Thumb mode, not one.
llvm-svn: 127840
2011-03-17 23:52:05 +00:00
Jim Grosbach bb0547d9c4 Pseudo-ize VMOVDcc and VMOVScc.
llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Jim Grosbach 9f2b3b569b 80 columns
llvm-svn: 127505
2011-03-11 23:00:16 +00:00
Jim Grosbach c77dea7f55 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
and VDUPLN32d, respectively.

llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach fa56bca781 Properly pseudo-ize ARM MVNCCi.
llvm-svn: 127482
2011-03-11 19:55:55 +00:00
Jim Grosbach d025498271 Properly pseudo-ize ARM MOVCCi and MOVCCi16.
llvm-svn: 127442
2011-03-11 01:09:28 +00:00
Jim Grosbach 62a7b473af Properly pseudo-ize MOVCCr and MOVCCs.
llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Anton Korobeynikov e7410dd0d5 Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

llvm-svn: 127101
2011-03-05 18:43:32 +00:00
Owen Anderson 4ebf471c9b Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
llvm-svn: 125127
2011-02-08 22:39:40 +00:00
Bob Wilson a609b8954e Change VLD3/4 and VST3/4 for quad registers to not update the address register.
These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used.  In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.

llvm-svn: 125013
2011-02-07 17:43:15 +00:00
Ted Kremenek 3c4408ceb6 Null initialize a few variables flagged by
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.

llvm-svn: 124073
2011-01-23 17:05:06 +00:00
Evan Cheng 2f2435d026 Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991
2011-01-21 18:55:51 +00:00
Evan Cheng b8b0ad80a8 Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905
2011-01-20 08:34:58 +00:00
Evan Cheng dfce83c8f5 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
2011-01-17 08:03:18 +00:00
Anton Korobeynikov 2f93128109 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
llvm-svn: 123170
2011-01-10 12:39:04 +00:00
Owen Anderson 9a4d42855d Revert r121721, which broke buildbots.
llvm-svn: 121726
2010-12-13 22:51:08 +00:00
Owen Anderson 4efa445f3c Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

llvm-svn: 121721
2010-12-13 22:29:52 +00:00
Bob Wilson 9b3546d877 Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

llvm-svn: 121718
2010-12-13 21:58:05 +00:00
Bob Wilson 157fec42c9 Use pseudo instructions for 2-register Neon instructions for scalar FP.
Partial fix for Radar 8711675.

llvm-svn: 121716
2010-12-13 21:05:52 +00:00
Matt Beaumont-Gay eb369f84ec Remove unused variables
llvm-svn: 121343
2010-12-09 01:04:43 +00:00
Bill Wendling f75412dec7 Remove extraneous semicolon.
llvm-svn: 121338
2010-12-09 00:51:54 +00:00
Jason W Kim e296ee830a Style nit and whitespace cleanup
llvm-svn: 121317
2010-12-08 23:35:25 +00:00
Jason W Kim ba8b6d9a1c Removed dead comment.
llvm-svn: 121313
2010-12-08 23:19:44 +00:00
Jason W Kim c79c5f6e8c ARM/MC/ELF TPsoft is now a proper pseudo inst.
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)

Also added support for ELF::R_ARM_TLS_IE32

llvm-svn: 121312
2010-12-08 23:14:44 +00:00
Owen Anderson 99ea8a3510 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
llvm-svn: 121082
2010-12-07 00:45:21 +00:00
Owen Anderson c1ee8e35d2 Revert r121021, which broke the buildbots.
llvm-svn: 121026
2010-12-06 18:57:40 +00:00
Jim Grosbach 67f13b19b5 Trailing whitespace.
llvm-svn: 121024
2010-12-06 18:47:44 +00:00
Owen Anderson bb4a76fc95 Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
llvm-svn: 121021
2010-12-06 18:35:51 +00:00
Jim Grosbach cdae9242fa When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,
not thumb2.

llvm-svn: 120711
2010-12-02 16:42:25 +00:00
Bob Wilson 431ac4ef50 Add support for NEON VLD3-dup instructions.
The encoding for alignment in VLD4-dup instructions is still a work in progress.

llvm-svn: 120356
2010-11-30 00:00:35 +00:00
Bob Wilson 77ab165afe Add support for NEON VLD3-dup instructions.
llvm-svn: 120312
2010-11-29 19:35:29 +00:00
Bob Wilson 2d790df105 Add support for NEON VLD2-dup instructions.
llvm-svn: 120236
2010-11-28 06:51:26 +00:00
Bob Wilson c92eea0175 Add NEON VLD1-dup instructions (load 1 element to all lanes).
llvm-svn: 120194
2010-11-27 06:35:16 +00:00
Benjamin Kramer 2e49eaa92f Avoid release build warnings.
llvm-svn: 119804
2010-11-19 16:36:02 +00:00
Anton Korobeynikov 0eecf5d201 Move hasFP() and few related hooks to TargetFrameInfo.
llvm-svn: 119740
2010-11-18 21:19:35 +00:00
Bill Wendling a68e3a5397 Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310
2010-11-16 01:16:36 +00:00
Evan Cheng 2bcb8daa44 Add conditional move of large immediate.
llvm-svn: 118968
2010-11-13 02:25:14 +00:00
Evan Cheng f478cf9685 Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
llvm-svn: 118938
2010-11-12 23:03:38 +00:00
Bob Wilson d80b29d6f7 Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
llvm-svn: 118069
2010-11-02 21:18:25 +00:00
Bob Wilson dc44990c7d Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
llvm-svn: 117964
2010-11-01 22:04:05 +00:00
Jim Grosbach 4a0c2d73c3 Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
2010-10-29 21:35:25 +00:00
Chandler Carruth 88c54b82c1 Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
until other LLVM projects using these are cleaned up.

llvm-svn: 117200
2010-10-23 08:10:43 +00:00
Duncan Sands b014abf3ef The return value of this call is not used, so no point
in assigning it to a variable (gcc-4.6 warning).

llvm-svn: 117024
2010-10-21 16:06:28 +00:00
Jim Grosbach 723159ef77 Fix backwards conditional.
llvm-svn: 116897
2010-10-20 01:10:01 +00:00
Jim Grosbach cb6fc2b2de Add dynamic realignment when rematerializing the base register.
llvm-svn: 116886
2010-10-20 00:02:50 +00:00
Jim Grosbach bbdc5d2ef9 Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879
2010-10-19 23:27:08 +00:00
Bob Wilson f1b3681ed0 Use simple RegState::Define flag instead of getDefRegState(true).
llvm-svn: 116601
2010-10-15 18:25:59 +00:00
Jim Grosbach d15723c22a When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
an explicit def. Make sure to capture that properly. rdar://8556556

llvm-svn: 116591
2010-10-15 17:35:17 +00:00
Jim Grosbach 8b6a9c1574 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534
2010-10-14 22:57:13 +00:00
Jim Grosbach 2e3e2a006b Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
pseudo instructions.

llvm-svn: 115840
2010-10-06 21:16:16 +00:00
Bob Wilson 450c6cfaff When expanding ARM pseudo registers, copy the existing predicate operands
instead of using default predicates on the expanded instructions.

llvm-svn: 114066
2010-09-16 04:25:37 +00:00
Bob Wilson 62c454847d Add missing break.
llvm-svn: 114048
2010-09-16 00:31:32 +00:00
Bob Wilson 6b853c3ce3 Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
register allocation to VLDMD and VSTMD respectively.  This avoids using the
dregpair operand modifier.

llvm-svn: 114047
2010-09-16 00:31:02 +00:00
Bob Wilson 62e9a052b9 Avoid warnings.
llvm-svn: 113857
2010-09-14 21:12:05 +00:00
Bob Wilson c597fd3b4a Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818
2010-09-13 23:55:10 +00:00
Bob Wilson d5c57a5ed4 Switch all the NEON vld-lane and vst-lane instructions over to the new
pseudo-instruction approach.  Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.

llvm-svn: 113812
2010-09-13 23:01:35 +00:00
Bob Wilson 84971c850a For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.

llvm-svn: 113456
2010-09-09 00:38:32 +00:00
Bob Wilson 4ccd5ce6ea Simplify copying over operands from pseudo NEON load/store instructions.
For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.

llvm-svn: 113452
2010-09-09 00:15:32 +00:00
Bob Wilson 359f8ba337 Clean up a comment.
llvm-svn: 113442
2010-09-08 23:39:54 +00:00
Bob Wilson 35fafca587 Finish converting the rest of the NEON VLD instructions to use pseudo-
instructions prior to regalloc.  Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.

llvm-svn: 112983
2010-09-03 18:16:02 +00:00
Bob Wilson 5a1df805e5 Fill in a missing comment.
llvm-svn: 112826
2010-09-02 16:17:29 +00:00
Bob Wilson 75a6408f88 Convert VLD1 and VLD2 instructions to use pseudo-instructions until
after regalloc.

llvm-svn: 112825
2010-09-02 16:00:54 +00:00
Anton Korobeynikov 48043d0173 Expand MOVi32imm in ARM mode after regalloc. This provides
scheduling opportunities (extra instruction can go in between
MOVT / MOVW pair removing the stall).

llvm-svn: 112546
2010-08-30 22:50:36 +00:00
Bob Wilson e2f8bdac14 When expanding NEON VST pseudo instructions, if the original super-register
operand is killed, add it to the expanded instruction as an implicit kill
operand instead of marking the individual subregs with kill flags.  This
should work better in general and also handles the case for VST3 where one
of the subregs was not referenced in the expanded instruction and so was
not marked killed.

llvm-svn: 112494
2010-08-30 18:10:48 +00:00
Bob Wilson 950882be07 Use pseudo instructions for VST1 and VST2.
llvm-svn: 112357
2010-08-28 05:12:57 +00:00
Bob Wilson 97919e9c59 Use pseudo instructions for VST3.
llvm-svn: 112208
2010-08-26 18:51:29 +00:00
Bob Wilson 4cec44975e Use pseudo instructions for VST1d64Q.
llvm-svn: 112170
2010-08-26 05:33:30 +00:00
Bob Wilson 9392b0e960 Start converting NEON load/stores to use pseudo instructions, beginning here
with the VST4 instructions.  Until after register allocation, we want to
represent sets of adjacent registers by a single super-register.  These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands.  Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.

llvm-svn: 112108
2010-08-25 23:27:42 +00:00
Owen Anderson a7aed18624 Reapply r110396, with fixes to appease the Linux buildbot gods.
llvm-svn: 110460
2010-08-06 18:33:48 +00:00
Owen Anderson bda59bd247 Revert r110396 to fix buildbots.
llvm-svn: 110410
2010-08-06 00:23:35 +00:00
Owen Anderson 755aceb5d0 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
2010-08-05 23:42:04 +00:00
Chris Lattner cbe9856fce prune #includes a little.
llvm-svn: 108929
2010-07-20 21:17:29 +00:00
Jim Grosbach 84511e1526 Clean up 80 column violations. No functional change.
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Jakob Stoklund Olesen 6c47d6423c Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h

llvm-svn: 104508
2010-05-24 16:54:32 +00:00
Evan Cheng 2f736c9577 Expand VMOVQQ into a pair of VMOVQ.
llvm-svn: 103684
2010-05-13 00:17:02 +00:00
Evan Cheng 7c1f56f29a Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
llvm-svn: 103667
2010-05-12 23:13:12 +00:00
Evan Cheng 5aa20d6c26 Remove a dead fixme.
llvm-svn: 103642
2010-05-12 20:20:22 +00:00
Dan Gohman bcaf681cde Add const qualifiers to CodeGen's use of LLVM IR constructs.
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
Chris Lattner a48f44d9ee improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!

llvm-svn: 90365
2009-12-03 00:50:42 +00:00
Anton Korobeynikov 2522908653 Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
2009-11-24 00:44:37 +00:00
Evan Cheng 207b246650 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
2009-11-06 23:52:48 +00:00