Commit Graph

271 Commits

Author SHA1 Message Date
Craig Topper 8cc904d65b [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need to make an iterator_range when we already have a function that returns an ArrayRef. NFC
llvm-svn: 258019
2016-01-17 20:38:18 +00:00
Craig Topper e5e035a3a8 Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
llvm-svn: 254843
2015-12-05 07:13:35 +00:00
David Majnemer f828a0ccc7 [WinEH] Make FuncletLayout more robust against catchret
Catchret transfers control from a catch funclet to an earlier funclet.
However, it is not completely clear which funclet the catchret target is
part of.  Make this clear by stapling the catchret target's funclet
membership onto the CATCHRET SDAG node.

llvm-svn: 249052
2015-10-01 18:44:59 +00:00
Hans Wennborg aa15bffa1f Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"
Except the changes that defined virtual destructors as =default, because that
ran into problems with GCC 4.7 and overriding methods that weren't noexcept.

llvm-svn: 247298
2015-09-10 16:49:58 +00:00
Hans Wennborg d2799a963f Revert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"
This caused build breakges, e.g.
http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/24926

llvm-svn: 247226
2015-09-10 00:57:26 +00:00
Hans Wennborg 6fa09455ed Fix Clang-tidy misc-use-override warnings, other minor fixes
Patch by Eugene Zelenko!

Differential Revision: http://reviews.llvm.org/D12740

llvm-svn: 247216
2015-09-10 00:12:56 +00:00
Owen Anderson abaa523e9e Add support for the convergent flag at the MC and MachineInstr levels.
llvm-svn: 238450
2015-05-28 18:33:39 +00:00
Owen Anderson ca5480062a Expand the Flags field of MCInstrDesc to 64 bits, while simultaneously
shrinking the Size and NumDefs fields to offset the size growth, and
reordering the fields to preserve a good packing.

This is necessary in the short term for adding a convergent flag, and
simultaneously future-proofs us against more flags being added in the
future.

llvm-svn: 238445
2015-05-28 18:03:07 +00:00
Michael Kuperstein db0712f986 Use std::bitset for SubtargetFeatures.
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures.
Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. 
This should now be fixed.

llvm-svn: 238192
2015-05-26 10:47:10 +00:00
Michael Kuperstein c3434b390d Reverting r237234, "Use std::bitset for SubtargetFeatures"
The buildbots are still not satisfied.
MIPS and ARM are failing (even though at least MIPS was expected to pass).

llvm-svn: 237245
2015-05-13 10:28:46 +00:00
Michael Kuperstein aba4a34ef2 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first two times this was committed (r229831, r233055), it caused several buildbot failures. 
At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed.

llvm-svn: 237234
2015-05-13 08:27:08 +00:00
James Y Knight e452e27129 Fix tablegen's PrintFatalError function to run registered file
cleanups.

Also, change code in tablegen which printed a message and then called
"exit(1)" to use PrintFatalError, instead.

This fixes instances where an empty output file was left behind after
a failed tablegen invocation, which would confuse subsequent ninja
runs into not attempting to rebuild.

Differential Revision: http://reviews.llvm.org/D9608

llvm-svn: 237058
2015-05-11 22:17:13 +00:00
Michael Kuperstein 29704e7fb4 Revert "Use std::bitset for SubtargetFeatures"
This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time.

llvm-svn: 233068
2015-03-24 12:56:59 +00:00
Michael Kuperstein 774b441b5e Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first time this was committed (r229831), it caused several buildbot failures. 
At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed.

Differential Revision: http://reviews.llvm.org/D8542

llvm-svn: 233055
2015-03-24 09:17:25 +00:00
Eric Christopher 44fd498a04 Use the variable names from the TargetInstrInfo source when we
reference them in the generated files. A few characters aren't huge
here and CFSetupOpcode is much more readable than S0.

llvm-svn: 232132
2015-03-13 01:26:39 +00:00
Eric Christopher 69c0a7c981 Add a return after the llvm namespace code for a little extra
readability in generated files.

llvm-svn: 232131
2015-03-13 01:10:08 +00:00
Eric Christopher 834d6420c1 Fix a couple of depedent->dependent typos.
llvm-svn: 230584
2015-02-26 00:00:33 +00:00
Michael Kuperstein efd7a96d2e Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.
llvm-svn: 229841
2015-02-19 11:38:11 +00:00
Michael Kuperstein ba5b04c798 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.

No functional change.

Differential Revision: http://reviews.llvm.org/D7065

llvm-svn: 229831
2015-02-19 09:01:04 +00:00
Tom Stellard 89b26108b1 Target: Allow target specific operand types
This adds two new fields to the RegisterOperand TableGen class:

string OperandNamespace = "MCOI";
string OperandType = "OPERAND_REGISTER";

These fields can be used to specify a target specific operand type,
which will be stored in the OperandType member of the MCOperandInfo
object.

This can be useful for targets that need to store some extra information
about operands that cannot be expressed using the target independent
types.  For example, in the R600 backend, there are operands which
can take either registers or immediates and it is convenient to be able
to specify this in the TableGen definitions.

llvm-svn: 225661
2015-01-12 19:33:09 +00:00
Craig Topper ca331bef51 Tablegen output formatting fixes.
llvm-svn: 222633
2014-11-23 09:40:10 +00:00
Quentin Colombet 7e3da6677a Add isInsertSubreg property.
This patch adds a new property: isInsertSubreg and the related target hooks:
TargetIntrInfo::getInsertSubregInputs and
TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific
instruction is a (kind of) INSERT_SUBREG.

The approach is similar to r215394.

<rdar://problem/12702965>

llvm-svn: 216139
2014-08-20 23:49:36 +00:00
Quentin Colombet 7e75cbaf47 Add isExtractSubreg property.
This patch adds a new property: isExtractSubreg and the related target hooks:
TargetIntrInfo::getExtractSubregInputs and
TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific
instruction is a (kind of) EXTRACT_SUBREG.

The approach is similar to r215394.

<rdar://problem/12702965>

llvm-svn: 216130
2014-08-20 21:51:26 +00:00
Quentin Colombet d533cdf26f Add isRegSequence property.
This patch adds a new property: isRegSequence and the related target hooks: 
TargetIntrInfo::getRegSequenceInputs and 
TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific
instruction is a (kind of) REG_SEQUENCE.

<rdar://problem/12702965>

llvm-svn: 215394
2014-08-11 22:17:14 +00:00
Matt Arsenault 41e148169d Make getNamedOperandIdx readonly
llvm-svn: 214524
2014-08-01 17:00:27 +00:00
Craig Topper 948dfbf3c4 [C++11] Use 'nullptr' in tablegen output files.
llvm-svn: 207611
2014-04-30 05:53:35 +00:00
Jim Grosbach 5198f3e988 c++11: Tidy up tblgen w/ range loops.
IntrInfoEmitter cleanup.

llvm-svn: 206553
2014-04-18 02:09:07 +00:00
Craig Topper 65efcb4685 Fix a vector that was passed by value instead of reference.
llvm-svn: 200827
2014-02-05 07:27:49 +00:00
Juergen Ributzka d12ccbd343 [weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

llvm-svn: 195064
2013-11-19 00:57:56 +00:00
Alexey Samsonov 49109a279c Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
  Base *foo = new Child();
  delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.

llvm-svn: 194997
2013-11-18 09:31:53 +00:00
Ahmed Bougacha 31377593bc TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.
llvm-svn: 194978
2013-11-17 21:24:41 +00:00
Juergen Ributzka dbedae89b9 [weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

llvm-svn: 194865
2013-11-15 22:34:48 +00:00
Joey Gouly 0e76fa7df5 Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.

llvm-svn: 190598
2013-09-12 10:28:05 +00:00
Vincent Lejeune 7deccf0f06 TableGen: Enumerate Schedule Model too.
llvm-svn: 189839
2013-09-03 19:43:28 +00:00
Tim Northover 421804420d ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.

TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.

llvm-svn: 188995
2013-08-22 09:57:11 +00:00
Tom Stellard 0ebf29d41f Revert "TableGen: Enumerate Schedule Model too."
This reverts commit 2ca1e4a39c7e0d7a00e66ff5437c6d7ace2404a0.

llvm-svn: 187525
2013-07-31 20:43:08 +00:00
Vincent Lejeune 22e6ddd475 TableGen: Enumerate Schedule Model too.
llvm-svn: 187511
2013-07-31 19:31:20 +00:00
Aaron Ballman e59e358823 Teaching llvm-tblgen to not emit a switch statement when there are no case statements.
llvm-svn: 186330
2013-07-15 16:53:32 +00:00
Tom Stellard b162d94871 TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.

In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.

For example, if you have an instruction like:

def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;

You can look up the operand indices using the new function, like this:

Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst)  => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2

The operand names are case sensitive, so $dst and $DST are considered
different operands.

This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values.  These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.

llvm-svn: 184879
2013-06-25 21:22:09 +00:00
Chandler Carruth 91d19d8e93 Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
2012-12-04 10:37:14 +00:00
Jakob Stoklund Olesen 9de596e650 Remove all references to TargetInstrInfoImpl.
This class has been merged into its super-class TargetInstrInfo.

llvm-svn: 168760
2012-11-28 02:35:17 +00:00
Joerg Sonnenberger 635debe85b Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 

llvm-svn: 166712
2012-10-25 20:33:17 +00:00
Sebastian Pop 5c87daf2c8 add TableGen support to create relationship maps between instructions
Relationship maps are represented as InstrMapping records which are parsed by
TableGen and the information is used to construct mapping tables to represent
appropriate relations between instructions. These tables are emitted into
XXXGenInstrInfo.inc file along with the functions to query them.

Patch by Jyotsna Verma <jverma@codeaurora.org>.

llvm-svn: 166685
2012-10-25 15:54:06 +00:00
Richard Trieu 2448969d7f Change (!list.size() == 0) to (!list.empty()). No functional change.
llvm-svn: 165812
2012-10-12 17:57:35 +00:00
Sean Silva 88eb8dd4ed tblgen: Use semantically correct RTTI functions.
Also, some minor cleanup.

llvm-svn: 165647
2012-10-10 20:24:47 +00:00
Sean Silva fb509ed156 tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

llvm-svn: 165646
2012-10-10 20:24:43 +00:00
Andrew Trick a88f1bddc6 TableGen subtarget emitter. Use getSchedClassIdx.
llvm-svn: 164096
2012-09-18 03:55:55 +00:00
Andrew Trick 8e7f202e32 Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072
2012-09-17 23:00:42 +00:00
Andrew Trick 36e07eb83e TableGen subtarget emitter. Use getSchedClassIdx.
llvm-svn: 164063
2012-09-17 22:19:01 +00:00
Jakob Stoklund Olesen 2382d320b3 Add an MCID::Select flag and TII hooks for optimizing selects.
Select instructions pick one of two virtual registers based on a
condition, like x86 cmov. On targets like ARM that support predication,
selects can sometimes be eliminated by predicating the instruction
defining one of the operands.

Teach PeepholeOptimizer to recognize select instructions, and ask the
target to optimize them.

llvm-svn: 162059
2012-08-16 23:11:47 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
2012-07-07 04:00:00 +00:00
Jakob Stoklund Olesen e6aed139f0 Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

llvm-svn: 158311
2012-06-11 15:37:55 +00:00
Jim Grosbach dac4a95b35 Tidy up. Whitespace.
llvm-svn: 154531
2012-04-11 21:02:30 +00:00
Craig Topper 91773ab2ca Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions.
llvm-svn: 153841
2012-04-01 18:14:14 +00:00
Benjamin Kramer b0640db80e Include cstdio in a few place that depended on getting it transitively through StringExtras.h
llvm-svn: 153328
2012-03-23 11:35:30 +00:00
Jakob Stoklund Olesen e3084895d2 Revert r152202: "Use uint16_t to store InstrNameIndices in MCInstrInfo."
We cannot limit the concatenated instruction names to 64K.  ARM is
already at 32K, and it is easy to imagine a target with more
instructions.

llvm-svn: 152817
2012-03-15 18:05:57 +00:00
Craig Topper b358499b18 Shrink and reorder some fields in MCOperandInfo to fit it in 8 bytes to reduce size of static tables.
llvm-svn: 152524
2012-03-11 01:57:56 +00:00
Craig Topper 5a4bcc749a Use uint16_t to store instruction implicit uses and defs. Reduces static data.
llvm-svn: 152301
2012-03-08 08:22:45 +00:00
Craig Topper d31658d44c Re-commit r152202 hopefully fixing the MSVC linker error.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.

llvm-svn: 152296
2012-03-08 06:55:27 +00:00
Chad Rosier 3048107bc1 Revert r152202 as it's causing internal buildbot failures.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect 
all 16-bit string table offsets. Also make sure the string to offset table 
string is not larger than 65536 characters since larger string literals aren't 
portable.

llvm-svn: 152233
2012-03-07 17:06:40 +00:00
Craig Topper 8d68422121 Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
llvm-svn: 152202
2012-03-07 05:17:23 +00:00
Benjamin Kramer bf152d57a4 Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.
Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

llvm-svn: 150245
2012-02-10 13:18:44 +00:00
Benjamin Kramer 8e012f5f22 Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per entry on x86_64.
No change on i386.

llvm-svn: 150170
2012-02-09 11:25:09 +00:00
Benjamin Kramer 0d6d098841 Move various generated tables into read-only memory, fixing up const correctness along the way.
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
Peter Collingbourne 84c287e33c Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
2011-10-01 16:41:13 +00:00
Jakob Stoklund Olesen df977fedb6 Add target hook for pseudo instruction expansion.
Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

llvm-svn: 140472
2011-09-25 19:21:35 +00:00
Andrew Trick 52363bdbeb Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160
2011-09-20 18:22:31 +00:00
Andrew Trick 8586e62d91 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
2011-09-20 03:17:40 +00:00
Evan Cheng e6fba77971 Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810
2011-08-30 19:09:48 +00:00
David Greene af8ee2cdee Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
2011-07-29 22:43:06 +00:00
David Greene 1aa0e3e118 [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
2011-07-29 19:07:05 +00:00
NAKAMURA Takumi cb1a888fde Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

llvm-svn: 135269
2011-07-15 12:50:21 +00:00
Benjamin Kramer c8dc46bc01 Add a new field to MCOperandInfo that contains information about the type of the Operand.
- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.

llvm-svn: 135197
2011-07-14 21:47:18 +00:00
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
2011-07-14 20:59:42 +00:00
Owen Anderson 651b230ca0 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Eric Christopher 71520a867d Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

llvm-svn: 134936
2011-07-11 23:06:52 +00:00
David Greene af973b4f36 [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
2011-07-11 18:25:51 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
2011-07-01 20:45:01 +00:00
Evan Cheng 703a0fbf39 Hide the call to InitMCInstrInfo into tblgen generated ctor.
llvm-svn: 134244
2011-07-01 17:57:27 +00:00
Evan Cheng df8974ef2f Add MCInstrInfo registeration machinery.
llvm-svn: 134026
2011-06-28 20:29:03 +00:00
Evan Cheng 1e210d08d8 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
llvm-svn: 134024
2011-06-28 20:07:07 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Evan Cheng 105974d497 Remove RCBarriers from TargetInstrDesc.
llvm-svn: 133964
2011-06-27 23:47:21 +00:00
Owen Anderson a84be6c96b Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.

llvm-svn: 133940
2011-06-27 21:06:21 +00:00
Jakob Stoklund Olesen d7bc5c26ab Give CodeGenRegisterClass a real sorted member set.
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

llvm-svn: 133040
2011-06-15 04:50:36 +00:00
Evan Cheng 880e299dcd - Add "Bitcast" target instruction property for instructions which perform
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.

llvm-svn: 127667
2011-03-15 05:09:26 +00:00
Evan Cheng 7f8ab6ee8b Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548
2010-11-17 20:13:28 +00:00
Chris Lattner d8adec70f3 factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
2010-11-01 04:03:32 +00:00
Owen Anderson 2c5df619c4 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710
2010-09-23 23:45:25 +00:00
Owen Anderson 6e0e8d7d64 Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
Not intended functionality change, as nothing uses this yet.

llvm-svn: 114702
2010-09-23 22:44:10 +00:00
Bill Wendling 18e853f458 Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all.

llvm-svn: 110531
2010-08-08 01:49:35 +00:00
Bill Wendling e8bb340203 Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't
need the Compare flag after all.

--- Reverse-merging r109901 into '.':
U    include/llvm/Target/TargetInstrDesc.h
U    include/llvm/Target/Target.td
U    utils/TableGen/InstrInfoEmitter.cpp
U    utils/TableGen/CodeGenInstruction.cpp
U    utils/TableGen/CodeGenInstruction.h

llvm-svn: 110424
2010-08-06 01:36:09 +00:00
Bill Wendling 9b8d586039 Add a "Compare" flag to the target instruction descriptor. This will be used
later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.

llvm-svn: 109901
2010-07-30 22:48:39 +00:00
Dan Gohman 882bb2984e Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296
2010-06-18 18:13:55 +00:00
Eric Christopher 223c481b1c How about ULL...
llvm-svn: 105726
2010-06-09 16:16:48 +00:00
Bruno Cardoso Lopes c2f87b7bb2 Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.

llvm-svn: 105652
2010-06-08 22:51:23 +00:00
Jakob Stoklund Olesen b93331f3be Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384
2010-04-05 03:10:20 +00:00
Jakob Stoklund Olesen f8d7eda663 Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

llvm-svn: 99539
2010-03-25 18:52:01 +00:00
Chris Lattner 1802b17b65 Finally change the instruction looking map to be a densemap from
record* -> instrinfo instead of std::string -> instrinfo.

This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug
build (20%).

llvm-svn: 98916
2010-03-19 01:07:44 +00:00
Chris Lattner 4763dbeaf6 make inst_begin/inst_end iterate over InstructionsByEnumValue.
Use CodeGenTarget::getInstNamespace in one place and fix it.

llvm-svn: 98915
2010-03-19 01:00:55 +00:00