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3230 Commits

Author SHA1 Message Date
Joerg Sonnenberger fc4789da4a Add support for the VIA PadLock instructions. 
llvm-svn: 128826
 2011-04-04 16:58:13 +00:00
Joerg Sonnenberger c94780c539 Use array_lengthof 
llvm-svn: 128823
 2011-04-04 16:25:38 +00:00
Joerg Sonnenberger fb3bce155e Change loops to derive the number of tables automatically 
llvm-svn: 128818
 2011-04-04 14:42:22 +00:00
Daniel Dunbar 5f74b39764 tlbgen/MC: StringRef's to temporary objects considered harmful. 
llvm-svn: 128735
 2011-04-01 20:23:52 +00:00
Andrew Trick 8a05f66139 Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables. 
llvm-svn: 128703
 2011-04-01 02:22:47 +00:00
Andrew Trick db6ed64529 whitespace 
llvm-svn: 128701
 2011-04-01 01:56:55 +00:00
Nick Lewycky 41198698aa Fix typo in generated HTML. 
llvm-svn: 128594
 2011-03-31 00:23:57 +00:00
Bob Wilson 271efda884 Use intrinsics for Neon vmull operations. Radar 9208957. 
llvm-svn: 128591
 2011-03-31 00:09:35 +00:00
Argyrios Kyrtzidis bcc3388252 ClangSAEmClangSACheckersEmitter, emit info about groups. 
llvm-svn: 128515
 2011-03-30 00:22:00 +00:00
Matt Beaumont-Gay bceec7f9a8 Quiet a gcc warning about changed name lookup rules 
llvm-svn: 128497
 2011-03-29 22:25:36 +00:00
Argyrios Kyrtzidis 42d0a6c770 In ClangSACheckersEmitter: 
- Also emit a list of packages and groups sorted by name
  - Avoid iterating over DenseSet so that the output of the arrays is deterministic.

llvm-svn: 128489
 2011-03-29 21:16:19 +00:00
Argyrios Kyrtzidis 2de9d572e8 For ClangSACheckersEmitter, allow a package to belong to checker group, in which all its checkers will go into the group. 
llvm-svn: 128474
 2011-03-29 18:53:00 +00:00
Devang Patel 94d1979a95 Remove scripts used by TEST=dbg from here. They now live inside llvm test suite. 
llvm-svn: 128425
 2011-03-28 20:28:30 +00:00
Duncan Sands d5f631cd2a Partially revert commit 127155: I think it is much more convenient 
to have structured log files rather than one big file produced by
piping output.

llvm-svn: 128378
 2011-03-27 13:52:32 +00:00
Douglas Gregor fa38bd3dfe Extend Clang's TableGen emitter for attributes to support bool arguments. 
llvm-svn: 128330
 2011-03-26 03:40:01 +00:00
Duncan Sands 5343a406f8 Useful script for finding regressions in the nightly testsuite. 
I think it was written by Pawel Worach.

llvm-svn: 128268
 2011-03-25 07:17:44 +00:00
Johnny Chen 72f4a95144 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. 
llvm-svn: 128249
 2011-03-25 00:17:42 +00:00
Johnny Chen ceef55466a The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since 
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.

llvm-svn: 128247
 2011-03-24 23:42:31 +00:00
Johnny Chen 73193f2475 The ARM disassembler was confused with the 16-bit tSTMIA instruction. 
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.

llvm-svn: 128246
 2011-03-24 23:21:14 +00:00
Bruno Cardoso Lopes f170f8bff6 Add asm parsing support w/ testcases for strex/ldrex family of instructions 
llvm-svn: 128236
 2011-03-24 21:04:58 +00:00
Johnny Chen 8bbc12824a ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. 
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234
 2011-03-24 20:42:48 +00:00
Douglas Gregor c5ed638408 Update the Clang attribute emitter to handle attributes of 'version' 
kind, and fix serialization/deserialization of IdentifierInfo
attributes. These are requires for the new 'availability' attribute.

llvm-svn: 128130
 2011-03-23 01:05:46 +00:00
Bill Wendling 1cd7bd62e4 Call static functions so that they aren't left unused. 
llvm-svn: 128020
 2011-03-21 21:08:27 +00:00
Bill Wendling 7e570b5ed8 A WIP commit of the InstAlias printing cleanup. This code will soon replace the 
code below it. Even though it looks very similar, it will match more precisely
and geneate better functions in the long run.

llvm-svn: 127991
 2011-03-21 08:59:17 +00:00
Bill Wendling 5d3174c102 Add the IAPrinter class. 
This is a helper class that will make it easier to say which InstAliases can be
printed and which cannot (because of ambiguity).

llvm-svn: 127990
 2011-03-21 08:40:31 +00:00
Bill Wendling 7e5771d7ce * Add classes that support the "feature" information. 
* Move the code that emits the reg in reg class matching into its own function.

llvm-svn: 127988
 2011-03-21 08:31:53 +00:00
Owen Anderson eb4b63d66e Thumb2 PC-relative loads require a fixup rather than just an immediate. 
llvm-svn: 127888
 2011-03-18 17:42:55 +00:00
NAKAMURA Takumi bac0d769cd raw_ostream: [PR6745] Tweak formatting (double)%e for Windows hosts. 
On MSVCRT and compatible, output of %e is incompatible to Posix by default. Number of exponent digits should be at least 2. "%+03d"

FIXME: Implement our formatter in future!
llvm-svn: 127872
 2011-03-18 09:30:10 +00:00
NAKAMURA Takumi 920139ca08 lit/ProgressBar.py: [PR7919] Improve line wrap for XN-incapable terminals. 
On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace.

llvm-svn: 127696
 2011-03-15 21:07:44 +00:00
Evan Cheng 880e299dcd - Add "Bitcast" target instruction property for instructions which perform 
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.

llvm-svn: 127667
 2011-03-15 05:09:26 +00:00
Sean Callanan c3fd523731 X86 table-generator and disassembler support for the AVX 
instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.

llvm-svn: 127644
 2011-03-15 01:23:15 +00:00
Owen Anderson 0fabf10388 Ignore isCodeGenOnly instructions when generating diassembly tables. 
llvm-svn: 127619
 2011-03-14 20:58:49 +00:00
Jim Grosbach 876ee079fc Trailing whitespace. 
llvm-svn: 127592
 2011-03-14 17:32:49 +00:00
Francois Pichet 0fc06eefad Correct small comment order typo. 
llvm-svn: 127575
 2011-03-14 02:30:32 +00:00
Jim Grosbach fcc34cacd9 Remove no-longer-correct special case for disasm of ARM BL instructions. 
llvm-svn: 127517
 2011-03-12 01:05:29 +00:00
Jim Grosbach f026d9ed53 Pseudo-ize the ARM 'B' instruction. 
llvm-svn: 127510
 2011-03-11 23:24:15 +00:00
Jim Grosbach 2fee5327aa Remove dead code. These ARM instruction definitions no longer exist. 
llvm-svn: 127509
 2011-03-11 23:15:02 +00:00
Jim Grosbach 376d5e8772 Remove dead code. These ARM instruction definitions no longer exist. 
llvm-svn: 127508
 2011-03-11 23:11:41 +00:00
Jim Grosbach bb0547d9c4 Pseudo-ize VMOVDcc and VMOVScc. 
llvm-svn: 127506
 2011-03-11 23:09:50 +00:00
Jim Grosbach 52594d99e4 Remove dead code. These ARM instruction definitions don't exist. 
llvm-svn: 127491
 2011-03-11 20:51:07 +00:00
Jim Grosbach 59eea670f8 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same 
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
 2011-03-11 20:44:08 +00:00
Jim Grosbach 6c609d626f Remove dead code. These ARM instruction definitions don't exist. 
llvm-svn: 127488
 2011-03-11 20:38:18 +00:00
Jim Grosbach c77dea7f55 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q 
and VDUPLN32d, respectively.

llvm-svn: 127486
 2011-03-11 20:31:17 +00:00
Jim Grosbach 24fe5e36ea ARM VREV64df and VREV64qf can just be patterns. The instruction is the same 
as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
 2011-03-11 20:18:05 +00:00
Jim Grosbach 730e1c2c9e Add missing 'return on failure'. Previously we'd crash after emitting 
the diagnostic.

llvm-svn: 127480
 2011-03-11 19:52:52 +00:00
Jim Grosbach f17b0031f3 Teach TableGen to pre-calculate register enum values when creating the 
CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.

rdar://9066491

llvm-svn: 127456
 2011-03-11 02:19:02 +00:00
Jim Grosbach eb52c23646 Make the register enum value part of the CodeGenRegister struct. 
llvm-svn: 127448
 2011-03-11 01:33:54 +00:00
Jim Grosbach f910bf29a9 Trailing whitespace. 
llvm-svn: 127447
 2011-03-11 01:27:24 +00:00
Jim Grosbach b1ac770fa3 Trailing whitespace. 
llvm-svn: 127446
 2011-03-11 01:19:05 +00:00
Jim Grosbach d0fc231e13 Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos. 
llvm-svn: 127445
 2011-03-11 01:16:49 +00:00