Commit Graph

316759 Commits

Author SHA1 Message Date
Simon Pilgrim 2c2f8e74b9 [X86][SSE] Match all-of bool scalar reductions into a bitcast/movmsk + cmp.
Same as what we do for vector reductions in combineHorizontalPredicateResult, use movmsk+cmp for scalar (and(extract(x,0),extract(x,1)) reduction patterns. 

llvm-svn: 361052
2019-05-17 17:25:55 +00:00
Sanjay Patel c05d85104d [InstCombine] add tests for insertelement with bitcasted operands; NFC
llvm-svn: 361051
2019-05-17 17:23:13 +00:00
Dmitri Gribenko 04323c24a1 Added an assertion to constant evaluation enty points that prohibits dependent expressions
Summary:
Constant evaluator does not work on value-dependent or type-dependent
expressions.

Also fixed bugs uncovered by these assertions.

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D61522

llvm-svn: 361050
2019-05-17 17:16:53 +00:00
Adrian Prantl 5d95b11b6b Update list of supported architectures.
llvm-svn: 361049
2019-05-17 17:05:23 +00:00
Matt Morehouse 012ef1cca7 [libFuzzer] Use SleepOneSecondTest.cpp for fork-sigusr.test.
ShallowOOMDeepCrash.cpp may hit libFuzzer's RSS limit before the SIGUSR2
is delivered, causing the test to be flaky when bots are under load.
SleepOneSecondTest.cpp will keep running until the signal is delivered.

llvm-svn: 361048
2019-05-17 16:56:01 +00:00
Cameron McInally 067e946859 [InstSimplify] Add unary fneg to `fsub 0.0, (fneg X) ==> X` transform
Differential Revision: https://reviews.llvm.org/D62013

llvm-svn: 361047
2019-05-17 16:47:00 +00:00
Jonas Devlieghere 777cad2c44 [Docs] Remove SVN checkout from LLDB build steps
This removes several older paragraphs in the LLDB build steps for Unix
systems which suggested checking out various components via SVN. Since
there's a separate page about getting the LLDB source which only
mentions Git, it seems appropriate to remove this older info from the
build docs.

Patch by: J. Ryan Stinnett

Differential revision: https://reviews.llvm.org/D62041

llvm-svn: 361046
2019-05-17 16:22:26 +00:00
Dmitry Preobrazhensky 198611b0ff [AMDGPU][MC] Corrected parsing of NAME:VALUE modifiers
See bug 41298: https://bugs.llvm.org/show_bug.cgi?id=41298

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D61009

llvm-svn: 361045
2019-05-17 16:04:17 +00:00
Roman Lebedev 64c756b991 [DAGCombiner] visitShiftByConstant(): drop bogus signbit check
Summary:
That check claims that the transform is illegal otherwise.
That isn't true:
1. For `ISD::ADD`, we only process `ISD::SHL` outer shift => sign bit does not matter
   https://rise4fun.com/Alive/K4A
2. For `ISD::AND`, there is no restriction on constants:
   https://rise4fun.com/Alive/Wy3
3. For `ISD::OR`, there is no restriction on constants:
   https://rise4fun.com/Alive/GOH
3. For `ISD::XOR`, there is no restriction on constants:
   https://rise4fun.com/Alive/ml6

So, why is it there then?

This changes the testcase that was touched by @spatel in rL347478,
but i'm not sure that test tests anything particular?

Reviewers: RKSimon, spatel, craig.topper, jojo, rengolin

Reviewed By: spatel

Subscribers: javed.absar, llvm-commits, spatel

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61918

llvm-svn: 361044
2019-05-17 15:52:58 +00:00
Roman Lebedev 3275060fe8 [InstCombine] canShiftBinOpWithConstantRHS(): drop bogus signbit check
Summary:
In D61918 i was looking at dropping it in DAGCombiner `visitShiftByConstant()`,
but as @craig.topper pointed out, it was copied from here.

That check claims that the transform is illegal otherwise.
That isn't true:
1. For `ISD::ADD`, we only process `ISD::SHL` outer shift => sign bit does not matter
   https://rise4fun.com/Alive/K4A
2. For `ISD::AND`, there is no restriction on constants:
   https://rise4fun.com/Alive/Wy3
3. For `ISD::OR`, there is no restriction on constants:
   https://rise4fun.com/Alive/GOH
3. For `ISD::XOR`, there is no restriction on constants:
   https://rise4fun.com/Alive/ml6

So, why is it there then?
As far as i can tell, it dates all the way back to original check-in rL7793.
I think we should just drop it.

Reviewers: spatel, craig.topper, efriedma, majnemer

Reviewed By: spatel

Subscribers: llvm-commits, craig.topper

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61938

llvm-svn: 361043
2019-05-17 15:52:49 +00:00
Kristof Umann 83cc1b35d1 [analyzer] Remove the default value arg from getChecker*Option
Since D57922, the config table contains every checker option, and it's default
value, so having it as an argument for getChecker*Option is redundant.

By the time any of the getChecker*Option function is called, we verified the
value in CheckerRegistry (after D57860), so we can confidently assert here, as
any irregularities detected at this point must be a programmer error. However,
in compatibility mode, verification won't happen, so the default value must be
restored.

This implies something else, other than adding removing one more potential point
of failure -- debug.ConfigDumper will always contain valid values for
checker/package options!

Differential Revision: https://reviews.llvm.org/D59195

llvm-svn: 361042
2019-05-17 15:52:13 +00:00
Russell Gallop 3a02b12439 Fix tests from r361013 on X86 bots.
llvm-svn: 361041
2019-05-17 15:38:01 +00:00
Dmitry Preobrazhensky 5ae3113969 [AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_fork
See https://bugs.llvm.org/show_bug.cgi?id=41888

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D62016

llvm-svn: 361040
2019-05-17 14:57:04 +00:00
Louis Dionne e92a9c99d6 [libcxxabi] Add a test for invalid assumptions on the alignment of exceptions
rdar://problem/49864414

llvm-svn: 361039
2019-05-17 14:53:29 +00:00
Simon Pilgrim 279314e81b [X86][AVX] Remove LowerCTTZ's AVX1 custom vector handling.
We can now rely on generic expansion to handle this.

llvm-svn: 361038
2019-05-17 14:37:19 +00:00
Yitzhak Mandelbaum 8369a9beb7 [LibTooling] Add support to Transformer for composing rules as an ordered choice.
This revision updates `RewriteRule` to support multiple subrules that are
interpreted as an ordered-choice (apply the first one that matches). With this
feature, users can write the rules that appear later in the list of subrules
knowing that previous rules' patterns *have not matched*, freeing them from
reasoning about those cases in the current pattern.

Reviewers: ilya-biryukov

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D61335

llvm-svn: 361037
2019-05-17 14:23:33 +00:00
Fangrui Song f3a3b93f54 [ELF] -r: fix R_*_NONE to section symbols on Elf*_Rel targets
On Elf*_Rel targets, for a relocation to a section symbol, an R_ABS is
added which will be used by relocateOne() to compute the implicit
addend.

Addends of R_*_NONE should be ignored, so don't emit an R_ABS.

This fixes crashes on X86 and ARM because their relocateOne() do not
handle R_*_NONE.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D62052

llvm-svn: 361036
2019-05-17 14:11:03 +00:00
Simon Pilgrim 62c7032c18 [X86][AVX] isNOT - add extract_subvector(xor X, -1) -> extract_subvector(X) fold.
Prep work for the removal of the remaining x86 CTTZ vector lowering.

llvm-svn: 361035
2019-05-17 14:04:56 +00:00
Stephen Kelly c8dcbed6e4 Extract ASTDumper to a header file
Summary:
This class has member APIs which are useful to clients.  Make it
possible to use those APIs without adding them to dump() member
functions.  Doing so does not scale.  The optional arguments to dump()
should be designed to be useful in a debugging context.

Reviewers: aaron.ballman

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D61835

llvm-svn: 361034
2019-05-17 13:59:15 +00:00
Stephen Kelly 0855896c68 Add a Visit overload for DynTypedNode to ASTNodeTraverser
Reviewers: aaron.ballman

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D61834

llvm-svn: 361033
2019-05-17 13:55:28 +00:00
Simon Pilgrim 10869e2962 Fix Wdocumentation warnings. NFCI.
llvm-svn: 361032
2019-05-17 13:42:16 +00:00
Dmitry Preobrazhensky 43fcc79837 [AMDGPU][MC] Enabled expressions for most operands which accept integer values
See bug 40873: https://bugs.llvm.org/show_bug.cgi?id=40873

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D60768

llvm-svn: 361031
2019-05-17 13:17:48 +00:00
Matt Arsenault 1a02d30c87 AMDGPU: Fix unused variable warnings in release builds
llvm-svn: 361030
2019-05-17 12:59:27 +00:00
Fangrui Song f3dccc64af [ELF] Don't align PT_TLS's p_memsz
The code was added in r252352, probably to address some layout issues.
Actually PT_TLS's p_memsz doesn't need to be aligned on either variant.
ld.bfd doesn't do that.

In case of larger alignment (e.g. 64 for Android Bionic on AArch64, see
D62055), this may make the overhead smaller.

Reviewed By: ruiu

Differential Revision: https://reviews.llvm.org/D62059

llvm-svn: 361029
2019-05-17 12:48:53 +00:00
Matt Arsenault a510b570c2 AMDGPU/GlobalISel: Legalize G_FCEIL
llvm-svn: 361028
2019-05-17 12:20:05 +00:00
Matt Arsenault 6aebcd5499 AMDGPU/GlobalISel: Legalize G_INTRINSIC_TRUNC
llvm-svn: 361027
2019-05-17 12:20:01 +00:00
Matt Arsenault 6aafc5e19d AMDGPU/GlobalISel: Legalize G_FRINT
llvm-svn: 361026
2019-05-17 12:19:57 +00:00
Matt Arsenault 1448f5689e AMDGPU/GlobalISel: Legalize G_FCOPYSIGN
llvm-svn: 361025
2019-05-17 12:19:52 +00:00
Clement Courbet 90900fbc9f [MergeICmps][NFC] Add more debug.
llvm-svn: 361024
2019-05-17 12:07:51 +00:00
Matt Arsenault 568f193847 AMDGPU/GlobalISel: RegBankSelect for llvm.amdgcn.s.buffer.load
llvm-svn: 361023
2019-05-17 12:02:34 +00:00
Matt Arsenault a3b5a386fa AMDGPU/GlobalISel: Use subreg index instead of extra unmerge
This saves instructions and extra steps, but I'm not sure about
introducing subregister indexes at this point.

llvm-svn: 361022
2019-05-17 12:02:31 +00:00
Matt Arsenault b3dc73634c AMDGPU/GlobalISel: Use waterfall loop for buffer_load
This adds support for more complex waterfall loops that need to handle
operands > 32-bits, and multiple operands.

llvm-svn: 361021
2019-05-17 12:02:27 +00:00
Matt Arsenault 1400a35f71 GlobalISel: Fix missing version of customFor
Add the list of pairs analagous, like legalFor and customFor has.

llvm-svn: 361020
2019-05-17 11:49:41 +00:00
Matt Arsenault e1a2a28d6b GlobalISel: Add fp<->int casts to MachineIRBuilder
llvm-svn: 361019
2019-05-17 11:49:39 +00:00
Matt Arsenault 7f8ea15ffa GlobalISel: Add MIRBuilder wrappers for bitcount instructions
Various expansions use these.

llvm-svn: 361018
2019-05-17 11:49:35 +00:00
Martin Storsjo 6ff6a8f656 [MinGW] Include --enable-auto-import in the help listing
Libtool concludes that the linker doesn't support shared libraries,
unless this flag is listed in the output of --help.

Differential Revision: https://reviews.llvm.org/D62053

llvm-svn: 361017
2019-05-17 11:07:46 +00:00
Martin Storsjo 6863dfaa21 [MinGW] Implement the -v and --version flags for the MinGW driver
Differential Revision: https://reviews.llvm.org/D62030

llvm-svn: 361016
2019-05-17 11:07:42 +00:00
Martin Storsjo 9ae0d222dc [MinGW] Implement --help for the MinGW driver
Differential Revision: https://reviews.llvm.org/D62029

llvm-svn: 361015
2019-05-17 11:07:38 +00:00
Martin Storsjo 2c52ddf31f [MinGW] Allow requesting PDB output without giving a file name
When integrating PDB output in mingw targeting build systems, it
might be a lot of extra work to specify unique file names for
the pdb output. Therefore allow omitting the actual file name
and let it implicitly be the same name as the linker output, with
a pdb extension.

As the current form of the pdb option takes a separate parameter value,
e.g. "-pdb out.pdb", it is impractical to leave out the parameter value.

Therefore, introduce a second syntax for the option, with an equals
sign, like -pdb=out.pdb, where the value easily can be omitted.

The form -pdb= for requesting pdb files with an implicit name should
work fine, even though it looks a bit unconventional in that form.

Differential Revision: https://reviews.llvm.org/D62004

llvm-svn: 361014
2019-05-17 11:07:33 +00:00
Fangrui Song ef9b8e03fd [ELF][test] Reorganize some R_*_NONE tests
Change R_{386,AARCH64}_NONE yaml2obj tests/icf10.test to use assembly

Add relocation-none-{arm,x86_64}.s.
  Check the referenced section survives under --gc-sections.
  Check -r copies R_X86_64_NONE R_AARCH64_NONE. (Elf*_Rel arches currently have a bug)
  Delete the dtrace tests as they are covered by the R_X86_64_NONE test.

Reviewed By: ruiu

Differential Revision: https://reviews.llvm.org/D62051

llvm-svn: 361013
2019-05-17 10:44:05 +00:00
Simon Pilgrim a6d3bd486b [X86] Pull out IsNOT helper. NFCI.
Return the input value for the NOT pattern: (xor X, -1) -> X

llvm-svn: 361012
2019-05-17 10:37:08 +00:00
Kristof Umann 85cf76e783 [analyzer] Validate checker option names and values
Validate whether the option exists, and also whether the supplied value is of
the correct type. With this patch, invoking the analyzer should be, at least
in the frontend mode, a lot safer.

Differential Revision: https://reviews.llvm.org/D57860

llvm-svn: 361011
2019-05-17 09:51:59 +00:00
Pavel Labath 62370dd0e0 minidump: Use MemoryList parsing code from llvm
llvm-svn: 361010
2019-05-17 09:47:34 +00:00
Clement Courbet 632dfdda16 Re-land r360859: "[MergeICmps] Simplify the code."
With a fix for PR41917: The predecessor list was changing under our feet.

-  for (BasicBlock *Pred : predecessors(EntryBlock_)) {
+  while (!pred_empty(EntryBlock_)) {
+    BasicBlock* const Pred = *pred_begin(EntryBlock_);

llvm-svn: 361009
2019-05-17 09:43:45 +00:00
Rhys Perry c4bc61bad7 [AMDGPU] detect WaW hazards when moving/merging load/store instructions
Summary:
    In order to combine memory operations efficiently, the load/store
    optimizer might move some instructions around. It's usually safe
    to move instructions down past the merged instruction because the
    pass checks if memory operations can be re-ordered.

    Though, the current logic doesn't handle Write-after-Write hazards.

    This fixes a reflection issue with Monster Hunter World and DXVK.

    v2: - rebased on top of master
        - clean up the test case
        - handle WaW hazards correctly

    Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=40130

Original patch by Samuel Pitoiset.

Reviewers: tpr, arsenm, nhaehnle

Reviewed By: nhaehnle

Subscribers: ronlieb, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D61313

llvm-svn: 361008
2019-05-17 09:32:23 +00:00
Ilya Biryukov 929af67361 [Lex] Allow to consume tokens while preprocessing
Summary:
By adding a hook to consume all tokens produced by the preprocessor.
The intention of this change is to make it possible to consume the
expanded tokens without re-runnig the preprocessor with minimal changes
to the preprocessor and minimal performance penalty when preprocessing
without recording the tokens.

The added hook is very low-level and reconstructing the expanded token
stream requires more work in the client code, the actual algorithm to
collect the tokens using this hook can be found in the follow-up change.

Reviewers: rsmith

Reviewed By: rsmith

Subscribers: eraman, nemanjai, kbarton, jsji, riccibruno, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D59885

llvm-svn: 361007
2019-05-17 09:32:05 +00:00
Kristof Umann 30b2307da8 [analyzer] Insert checker options into AnalyzerOption::ConfigTable
The more entries we have in AnalyzerOptions::ConfigTable, the more helpful
debug.ConfigDumper is. With this patch, I'm pretty confident that it'll now emit
the entire state of the analyzer, minus the frontend flags.

It would be nice to reserve the config table specifically to checker options
only, as storing the regular analyzer configs is kinda redundant.

Differential Revision: https://reviews.llvm.org/D57922

llvm-svn: 361006
2019-05-17 09:29:44 +00:00
Cullen Rhodes 7f605c3550 [AArch64][SVE2] Asm: add saturating multiply-add long instructions
Summary:
Patch adds support for indexed and unpredicated vectors forms of the
following instructions:

    * SQDMLALB, SQDMLALT, SQDMLSLB, SQDMLSLT

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D61997

llvm-svn: 361005
2019-05-17 09:29:43 +00:00
Sven van Haastregt 151d4f88dc [NFC] Fix line endings in OpenCL tests
llvm-svn: 361004
2019-05-17 09:25:38 +00:00
Cullen Rhodes 334130a199 [AArch64][SVE2] Asm: add integer multiply-add long instructions
Summary:
Patch adds support for indexed and unpredicated vectors forms of the
following instructions:

    * SMLALB, SMLALT, UMLALB, UMLALT, SMLSLB, SMLSLT, UMLSLB, UMLSLT

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: rovka

Differential Revision: https://reviews.llvm.org/D61951

llvm-svn: 361003
2019-05-17 09:19:41 +00:00