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20016 Commits

Author SHA1 Message Date
Hal Finkel 2ba61e47a9 64-bit LR8 load should use X11 not R11 
llvm-svn: 146021
 2011-12-07 06:32:37 +00:00
Jakob Stoklund Olesen 2f0400b780 Eliminate delta argument from AdjustBBOffsetsAfter. 
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

llvm-svn: 146018
 2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen 97c857199e Compute some alignment information for each basic block. 
These fields are not used for anything yet.

llvm-svn: 146017
 2011-12-07 04:17:35 +00:00
Jim Grosbach 2cf294a213 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
 2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen af748e1180 Move common expression into a method. 
llvm-svn: 146008
 2011-12-07 01:22:52 +00:00
Jim Grosbach 585ce30b8b ARM Implement ARM ARM Table A7-3 via TokenAlias. 
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

llvm-svn: 146007
 2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen e2b3ff2a07 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>. 
No functional change is intended.

llvm-svn: 146005
 2011-12-07 01:08:25 +00:00
Jim Grosbach d4b8249434 ARM: NEON SHLL instruction immediate operand range checking. 
llvm-svn: 146003
 2011-12-07 01:07:24 +00:00
Bruno Cardoso Lopes 61e6d987bf Add a few moreLocal/Global R_MIPS_GOT related fixups and 
make the addend fixup code a bit more generic

Patch by Jack Carter.

llvm-svn: 145998
 2011-12-07 00:28:57 +00:00
Jim Grosbach 47c24c2084 ARM: Parameterize the immediate operand type for NEON VSHLL. 
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

llvm-svn: 145994
 2011-12-07 00:02:17 +00:00
Jakob Stoklund Olesen cc6bfa8e79 Revert r145971: "Use conservative size estimate for tBR_JTr." 
This caused more offset errors.

llvm-svn: 145980
 2011-12-06 22:41:31 +00:00
Bill Wendling 67a70c995a Explicitly check for the different SUB instructions. 
llvm-svn: 145976
 2011-12-06 22:14:27 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support. 
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
 2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen 33fe130e12 Use conservative size estimate for tBR_JTr. 
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

llvm-svn: 145971
 2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen 2fa7448f31 Remove alignment from deserted constant islands. 
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.

This should fix the many Thumb1 assembler errors in the nightly test
suite.

The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.

<rdar://problem/10534709>

llvm-svn: 145970
 2011-12-06 21:55:35 +00:00
Bill Wendling 5a173cd367 Encode the total stack if there isn't a frame. 
llvm-svn: 145969
 2011-12-06 21:34:01 +00:00
Bill Wendling a73c0c99ea * Add a macro to remove a magic number. 
* Rename variables to reflect what they're actually used for.

llvm-svn: 145968
 2011-12-06 21:23:42 +00:00
Hal Finkel bde7f8ffe2 add RESTORE_CR and support CR unspills 
llvm-svn: 145961
 2011-12-06 20:55:36 +00:00
Hal Finkel 4ec02b02ac remove old FIXME 
llvm-svn: 145960
 2011-12-06 20:52:56 +00:00
Bill Wendling 87571b6392 Check the correct value for small stack sizes. Also modify some comments. 
llvm-svn: 145954
 2011-12-06 19:16:17 +00:00
Bill Wendling a4e87944a8 For a small sized stack, we encode that value directly with no "stack adjust" value. 
llvm-svn: 145952
 2011-12-06 19:09:06 +00:00
Justin Holewinski 04424665c3 PTX: Continue to fix up the register mess. 
llvm-svn: 145947
 2011-12-06 17:39:48 +00:00
Justin Holewinski 3063ac87aa PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols 
llvm-svn: 145946
 2011-12-06 17:39:46 +00:00
Craig Topper 83320e03e6 Add X86ISD::HADD/HSUB to getTargetNodeName 
llvm-svn: 145929
 2011-12-06 09:31:36 +00:00
Craig Topper 6572e0f203 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
llvm-svn: 145927
 2011-12-06 09:04:59 +00:00
Craig Topper 8d4ba198d6 Merge floating point and integer UNPCK X86ISD node types. 
llvm-svn: 145926
 2011-12-06 08:21:25 +00:00
Craig Topper 3cb802c775 Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs. 
llvm-svn: 145924
 2011-12-06 05:31:16 +00:00
Jim Grosbach e303e24d77 ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

llvm-svn: 145923
 2011-12-06 05:28:00 +00:00
Jim Grosbach 5f143be8c5 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
 2011-12-06 05:03:45 +00:00
Craig Topper bf41eb3a98 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
llvm-svn: 145921
 2011-12-06 04:59:07 +00:00
Jim Grosbach 175c7d0da5 Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
 2011-12-06 04:49:29 +00:00
Bruno Cardoso Lopes 0c24d8a406 Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter 
llvm-svn: 145912
 2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes 1b1a122b4c Add register HWR29 numbering. Patch by Jack Carter 
llvm-svn: 145910
 2011-12-06 03:34:36 +00:00
Bill Wendling 4e87e850a2 Add a comment. 
llvm-svn: 145896
 2011-12-06 01:57:48 +00:00
Jim Grosbach 425e180ce8 Tidy up value checking. 
llvm-svn: 145895
 2011-12-06 01:53:17 +00:00
NAKAMURA Takumi d3002490bf MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. 
llvm-svn: 145894
 2011-12-06 01:48:32 +00:00
Chad Rosier c77830d21e [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

llvm-svn: 145891
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen 2e05db2fa0 Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
 2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen 10e1252269 Use logarithmic units for basic block alignment. 
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

llvm-svn: 145889
 2011-12-06 01:26:19 +00:00
Bill Wendling f7cef7ecad The compact encoding of the registers are 3-bits each. Make sure we shift the 
value over that much.

llvm-svn: 145888
 2011-12-06 01:26:14 +00:00
Jim Grosbach 9105085b4a Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

llvm-svn: 145885
 2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen 2608157f79 Use an existing function. 
llvm-svn: 145883
 2011-12-06 00:51:12 +00:00
Jim Grosbach 25b63fa117 Move target-specific logic out of generic MCAssembler. 
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

llvm-svn: 145881
 2011-12-06 00:47:03 +00:00
Jim Grosbach 34a7c6dfd7 Simple branch relaxation for Thumb2 Bcc instructions. 
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

llvm-svn: 145871
 2011-12-05 23:45:46 +00:00
Jim Grosbach b8c719ccc6 Tweak ADDrr fix. Bad check for explicit .w 
llvm-svn: 145863
 2011-12-05 22:27:04 +00:00
Jim Grosbach e489babf9b Thumb2 prefer ADD register encoding T2 to T3 when possible. 
rdar://10529664

llvm-svn: 145860
 2011-12-05 22:16:39 +00:00
Akira Hatanaka 20cee2eba1 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
 2011-12-05 21:26:34 +00:00
Akira Hatanaka 9b8ac674bc Split ExtIns into two base classes and have instructions EXT and INS derive from 
them.

llvm-svn: 145852
 2011-12-05 21:14:28 +00:00
Jim Grosbach ec9ba98299 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348

llvm-svn: 145851
 2011-12-05 21:06:26 +00:00
Akira Hatanaka 34e3df76f9 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.

llvm-svn: 145850
 2011-12-05 21:03:03 +00:00