e53c95f180
fix PR9629 - We were lowering regexes like a{{b|c}}d into ab|cd, which
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is substantially different than a(b|c)d. Form the latter regex instead.
This found a few problems in the testsuite, which serves as its test.
llvm-svn: 129196
2011-04-09 06:37:03 +00:00
53e0679d6f
various cleanups, no functionality change.
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llvm-svn: 129192
2011-04-09 06:18:02 +00:00
33984c6973
Only emit the AvailableFeatures variable if it's used.
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llvm-svn: 129124
2011-04-08 04:08:57 +00:00
bc3f79044a
Replace the old algorithm that emitted the "print the alias for an instruction"
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with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.
There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.
llvm-svn: 129110
2011-04-07 21:20:06 +00:00
fc4789da4a
Add support for the VIA PadLock instructions.
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llvm-svn: 128826
2011-04-04 16:58:13 +00:00
c94780c539
Use array_lengthof
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llvm-svn: 128823
2011-04-04 16:25:38 +00:00
fb3bce155e
Change loops to derive the number of tables automatically
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llvm-svn: 128818
2011-04-04 14:42:22 +00:00
5f74b39764
tlbgen/MC: StringRef's to temporary objects considered harmful.
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llvm-svn: 128735
2011-04-01 20:23:52 +00:00
8a05f66139
Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables.
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llvm-svn: 128703
2011-04-01 02:22:47 +00:00
db6ed64529
whitespace
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llvm-svn: 128701
2011-04-01 01:56:55 +00:00
41198698aa
Fix typo in generated HTML.
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llvm-svn: 128594
2011-03-31 00:23:57 +00:00
271efda884
Use intrinsics for Neon vmull operations. Radar 9208957.
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llvm-svn: 128591
2011-03-31 00:09:35 +00:00
bcc3388252
ClangSAEmClangSACheckersEmitter, emit info about groups.
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llvm-svn: 128515
2011-03-30 00:22:00 +00:00
bceec7f9a8
Quiet a gcc warning about changed name lookup rules
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llvm-svn: 128497
2011-03-29 22:25:36 +00:00
42d0a6c770
In ClangSACheckersEmitter:
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- Also emit a list of packages and groups sorted by name
- Avoid iterating over DenseSet so that the output of the arrays is deterministic.
llvm-svn: 128489
2011-03-29 21:16:19 +00:00
2de9d572e8
For ClangSACheckersEmitter, allow a package to belong to checker group, in which all its checkers will go into the group.
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llvm-svn: 128474
2011-03-29 18:53:00 +00:00
94d1979a95
Remove scripts used by TEST=dbg from here. They now live inside llvm test suite.
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llvm-svn: 128425
2011-03-28 20:28:30 +00:00
d5f631cd2a
Partially revert commit 127155: I think it is much more convenient
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to have structured log files rather than one big file produced by
piping output.
llvm-svn: 128378
2011-03-27 13:52:32 +00:00
fa38bd3dfe
Extend Clang's TableGen emitter for attributes to support bool arguments.
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llvm-svn: 128330
2011-03-26 03:40:01 +00:00
5343a406f8
Useful script for finding regressions in the nightly testsuite.
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I think it was written by Pawel Worach.
llvm-svn: 128268
2011-03-25 07:17:44 +00:00
72f4a95144
delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.
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llvm-svn: 128249
2011-03-25 00:17:42 +00:00
ceef55466a
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since
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the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add
test cases for that.
llvm-svn: 128247
2011-03-24 23:42:31 +00:00
73193f2475
The ARM disassembler was confused with the 16-bit tSTMIA instruction.
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According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.
llvm-svn: 128246
2011-03-24 23:21:14 +00:00
f170f8bff6
Add asm parsing support w/ testcases for strex/ldrex family of instructions
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llvm-svn: 128236
2011-03-24 21:04:58 +00:00
8bbc12824a
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
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Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
2011-03-24 20:42:48 +00:00
c5ed638408
Update the Clang attribute emitter to handle attributes of 'version'
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kind, and fix serialization/deserialization of IdentifierInfo
attributes. These are requires for the new 'availability' attribute.
llvm-svn: 128130
2011-03-23 01:05:46 +00:00
1cd7bd62e4
Call static functions so that they aren't left unused.
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llvm-svn: 128020
2011-03-21 21:08:27 +00:00
7e570b5ed8
A WIP commit of the InstAlias printing cleanup. This code will soon replace the
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code below it. Even though it looks very similar, it will match more precisely
and geneate better functions in the long run.
llvm-svn: 127991
2011-03-21 08:59:17 +00:00
5d3174c102
Add the IAPrinter class.
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This is a helper class that will make it easier to say which InstAliases can be
printed and which cannot (because of ambiguity).
llvm-svn: 127990
2011-03-21 08:40:31 +00:00
7e5771d7ce
* Add classes that support the "feature" information.
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* Move the code that emits the reg in reg class matching into its own function.
llvm-svn: 127988
2011-03-21 08:31:53 +00:00
eb4b63d66e
Thumb2 PC-relative loads require a fixup rather than just an immediate.
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llvm-svn: 127888
2011-03-18 17:42:55 +00:00
bac0d769cd
raw_ostream: [PR6745] Tweak formatting (double)%e for Windows hosts.
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On MSVCRT and compatible, output of %e is incompatible to Posix by default. Number of exponent digits should be at least 2. "%+03d"
FIXME: Implement our formatter in future!
llvm-svn: 127872
2011-03-18 09:30:10 +00:00
920139ca08
lit/ProgressBar.py: [PR7919] Improve line wrap for XN-incapable terminals.
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On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace.
llvm-svn: 127696
2011-03-15 21:07:44 +00:00
880e299dcd
- Add "Bitcast" target instruction property for instructions which perform
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nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.
llvm-svn: 127667
2011-03-15 05:09:26 +00:00
c3fd523731
X86 table-generator and disassembler support for the AVX
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instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
llvm-svn: 127644
2011-03-15 01:23:15 +00:00
0fabf10388
Ignore isCodeGenOnly instructions when generating diassembly tables.
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llvm-svn: 127619
2011-03-14 20:58:49 +00:00
876ee079fc
Trailing whitespace.
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llvm-svn: 127592
2011-03-14 17:32:49 +00:00
0fc06eefad
Correct small comment order typo.
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llvm-svn: 127575
2011-03-14 02:30:32 +00:00
fcc34cacd9
Remove no-longer-correct special case for disasm of ARM BL instructions.
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llvm-svn: 127517
2011-03-12 01:05:29 +00:00
f026d9ed53
Pseudo-ize the ARM 'B' instruction.
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llvm-svn: 127510
2011-03-11 23:24:15 +00:00
2fee5327aa
Remove dead code. These ARM instruction definitions no longer exist.
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llvm-svn: 127509
2011-03-11 23:15:02 +00:00
376d5e8772
Remove dead code. These ARM instruction definitions no longer exist.
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llvm-svn: 127508
2011-03-11 23:11:41 +00:00
bb0547d9c4
Pseudo-ize VMOVDcc and VMOVScc.
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llvm-svn: 127506
2011-03-11 23:09:50 +00:00
52594d99e4
Remove dead code. These ARM instruction definitions don't exist.
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llvm-svn: 127491
2011-03-11 20:51:07 +00:00
59eea670f8
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
6c609d626f
Remove dead code. These ARM instruction definitions don't exist.
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llvm-svn: 127488
2011-03-11 20:38:18 +00:00
c77dea7f55
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
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and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
24fe5e36ea
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
730e1c2c9e
Add missing 'return on failure'. Previously we'd crash after emitting
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the diagnostic.
llvm-svn: 127480
2011-03-11 19:52:52 +00:00
f17b0031f3
Teach TableGen to pre-calculate register enum values when creating the
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CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.
rdar://9066491
llvm-svn: 127456
2011-03-11 02:19:02 +00:00
Chris Lattner