llvm-project

Commit Graph

Author	SHA1	Message	Date
Hiroshi Inoue	4ba87d01bc	fix formatting; NFC llvm-svn: 307662	2017-07-11 15:41:31 +00:00
Hiroshi Inoue	df6a0fb8a7	[PowerPC] fix latency for simple integer instructions in POWER9 scheduler In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions. This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion. Differential Revision: https://reviews.llvm.org/D34869 llvm-svn: 307624	2017-07-11 05:37:16 +00:00
Ehsan Amiri	6c17bb0eb7	[Power9] Processor Model for Scheduling PWR9 processor model for instruction scheduling. A subsequent patch will migrate PWR9 to Post RA MIScheduler. https://reviews.llvm.org/D24525 llvm-svn: 290102	2016-12-19 13:35:45 +00:00

Author

SHA1

Message

Date

Hiroshi Inoue

4ba87d01bc

fix formatting; NFC

llvm-svn: 307662

2017-07-11 15:41:31 +00:00

Hiroshi Inoue

df6a0fb8a7

[PowerPC] fix latency for simple integer instructions in POWER9 scheduler

In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions.
This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion.

Differential Revision: https://reviews.llvm.org/D34869

llvm-svn: 307624

2017-07-11 05:37:16 +00:00

Ehsan Amiri

6c17bb0eb7

[Power9] Processor Model for Scheduling

PWR9 processor model for instruction scheduling. A subsequent patch will migrate
PWR9 to Post RA MIScheduler.
https://reviews.llvm.org/D24525

llvm-svn: 290102

2016-12-19 13:35:45 +00:00

3 Commits