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135 Commits

Author SHA1 Message Date
Akira Hatanaka 8782734bcc Test cases for 64-bit load and store instructions. 
llvm-svn: 141631
 2011-10-11 01:52:31 +00:00
Akira Hatanaka 6c71ef32be Move CHECK after entry label. 
llvm-svn: 141030
 2011-10-03 21:24:30 +00:00
Akira Hatanaka c3a6357ee3 Add support for 64-bit logical NOR. 
llvm-svn: 141029
 2011-10-03 21:23:18 +00:00
Akira Hatanaka 48a72ca0cb Add support for 64-bit count leading ones and zeros instructions. 
llvm-svn: 141028
 2011-10-03 21:16:50 +00:00
Akira Hatanaka b1538f91dc Add support for 64-bit divide instructions. 
llvm-svn: 141024
 2011-10-03 21:06:13 +00:00
Akira Hatanaka a279d9bd6a Add support for 64-bit integer multiply instructions. 
llvm-svn: 141017
 2011-10-03 20:01:11 +00:00
Akira Hatanaka 1fef284cf9 Remove unnecessary checking of register operands. 
llvm-svn: 140872
 2011-09-30 19:18:24 +00:00
Akira Hatanaka 7ba8a8d656 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Akira Hatanaka b381129095 Check values of immediate operands. 
llvm-svn: 140860
 2011-09-30 17:19:21 +00:00
Akira Hatanaka 61e256aa69 Mips64 shift instructions. 
llvm-svn: 140841
 2011-09-30 03:18:46 +00:00
Akira Hatanaka 7769a77710 Mips64 arithmetic and logical instructions with one source register and 
immediate.

llvm-svn: 140839
 2011-09-30 02:08:54 +00:00
Akira Hatanaka f2619ee3ff Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140825
 2011-09-29 23:52:13 +00:00
Akira Hatanaka 36036412e2 Mips64 arithmetic and logical instructions with two source registers. 
llvm-svn: 140806
 2011-09-29 20:37:56 +00:00
Eli Friedman c064f2c33e Convert more tests over to the new atomic instructions. 
llvm-svn: 140559
 2011-09-26 20:27:49 +00:00
Akira Hatanaka 4ce4a61cac Remove +. 
llvm-svn: 140266
 2011-09-21 17:43:48 +00:00
Akira Hatanaka 24b6588743 Re-enable some of the disabled tests. Use FileCheck instead of grep to check 
output.

llvm-svn: 140263
 2011-09-21 17:36:30 +00:00
Akira Hatanaka 73b5d6ddc1 Delete test cases that generate code for allegrex/psp and cannot be repurposed. 
llvm-svn: 139652
 2011-09-13 22:29:13 +00:00
Akira Hatanaka fba4bd62b1 Add pattern used to match MipsLo, which is needed when the instruction selector 
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead

llvm-svn: 139634
 2011-09-13 20:13:58 +00:00
Akira Hatanaka f58d6812a9 Disable tests which generate code for allegrex or psp. 
llvm-svn: 139632
 2011-09-13 20:00:35 +00:00
Akira Hatanaka 5624707684 Fix test cases. 
Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433
 2011-09-09 23:14:58 +00:00
Akira Hatanaka 4444daeec5 Drop support for Mips1 and Mips2. 
llvm-svn: 139405
 2011-09-09 20:45:50 +00:00
Akira Hatanaka d22a1c6c95 Drop support for Allegrex. Allegrex implements a variant of Mips2. 
llvm-svn: 139383
 2011-09-09 19:00:51 +00:00
Akira Hatanaka df1df7edf1 Change default target architecture from Mips1 to Mips32r1 in preparation for 
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344
 2011-09-09 01:13:27 +00:00
Nick Lewycky 474c455060 Disable these tests harder. They're XFAIL'd, but that means they still run, and 
these tests all infinitely recurse, bringing my system down into swapping hell.

llvm-svn: 139192
 2011-09-06 22:08:18 +00:00
Bill Wendling 912668d998 Better fix for this testcase. Update it to the new EH scheme entirely. 
llvm-svn: 139039
 2011-09-02 21:27:08 +00:00
Bill Wendling 17706bcffb Update for new EH stuff. (I'm not sure if this is 100% correct.) 
llvm-svn: 139038
 2011-09-02 21:24:17 +00:00
Dan Gohman 3767be9aee Revert r131152, r129796, r129761. This code is currently considered 
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977
 2011-09-01 23:07:08 +00:00
Akira Hatanaka fb4161ae88 Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Akira Hatanaka 5360f88355 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Akira Hatanaka 7d7bec5acf Add test case for r137711. 
llvm-svn: 137725
 2011-08-16 17:32:01 +00:00
Akira Hatanaka 2263c10946 Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
 2011-08-16 03:51:51 +00:00
Akira Hatanaka 2fcc1cfdce Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Akira Hatanaka 2f6b944f56 Test case for 137484 
llvm-svn: 137486
 2011-08-12 18:12:06 +00:00
Akira Hatanaka 79d60d0e94 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 

llvm-svn: 137378
 2011-08-11 22:42:31 +00:00
Akira Hatanaka a4c09bce9b Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Akira Hatanaka f3b29992d5 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
 2011-07-19 20:34:00 +00:00
Akira Hatanaka e450358a21 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka 338879a7f4 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
llvm-svn: 135418
 2011-07-18 19:58:59 +00:00
Akira Hatanaka 27292638bd Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
 2011-07-18 18:52:12 +00:00
Akira Hatanaka 35792089e7 Change the chain input of nodes that load the address of a function. This change 
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811
 2011-06-24 19:01:25 +00:00
Akira Hatanaka ca88b4abec Prevent generation of redundant addiu instructions that compute address of 
static variables or functions. 

llvm-svn: 133803
 2011-06-24 17:55:19 +00:00
Akira Hatanaka 4c406e7457 Re-apply 132758 and 132768 which were speculatively reverted in 132777. 
llvm-svn: 133494
 2011-06-21 00:40:49 +00:00
Chris Lattner 5756c16cdf make the asmparser reject function and type redefinitions. 'Merging' hasn't been 
needed since llvm-gcc 3.4 days.

llvm-svn: 133248
 2011-06-17 07:06:44 +00:00
Chris Lattner b90ed2233c manually upgrade a bunch of tests to modern syntax, and remove some that 
are either unreduced or only test old syntax.

llvm-svn: 133228
 2011-06-17 03:14:27 +00:00
Eric Christopher f15601f19a Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
llvm-svn: 132777
 2011-06-09 16:03:19 +00:00
Akira Hatanaka 0683a7212e Initial support for inline asm memory operand constraints. 
llvm-svn: 132768
 2011-06-09 03:31:05 +00:00
Akira Hatanaka 4e9af454f7 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the 
dynamically allocated stack area was not set.

llvm-svn: 132758
 2011-06-08 21:28:09 +00:00
Akira Hatanaka 08b7a779ef Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: 
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703
 2011-06-07 02:17:21 +00:00
Akira Hatanaka 2446869410 Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic. 
llvm-svn: 132448
 2011-06-02 01:03:14 +00:00
Akira Hatanaka d84c76f2a7 Test case for r132444. 
llvm-svn: 132445
 2011-06-02 00:25:53 +00:00