Commit Graph

1079 Commits

Author SHA1 Message Date
Gabor Buella 8701b18a25 [X86] Split up -march=icelake to -client & -server
Reviewers: craig.topper, zvi, echristo

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45056

llvm-svn: 329741
2018-04-10 18:58:26 +00:00
Gabor Buella 5966507c4e [X86] Disable SGX for Skylake Server - CPP test
Summary: Fix test case - corresponding to r329701

Reviewers: craig.topper, davezarzycki

Reviewed By: davezarzycki

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D45488

llvm-svn: 329710
2018-04-10 15:03:03 +00:00
Alexander Kornienko 2a8c18d991 Fix typos in clang
Found via codespell -q 3 -I ../clang-whitelist.txt
Where whitelist consists of:

  archtype
  cas
  classs
  checkk
  compres
  definit
  frome
  iff
  inteval
  ith
  lod
  methode
  nd
  optin
  ot
  pres
  statics
  te
  thru

Patch by luzpaz! (This is a subset of D44188 that applies cleanly with a few
files that have dubious fixes reverted.)

Differential revision: https://reviews.llvm.org/D44188

llvm-svn: 329399
2018-04-06 15:14:32 +00:00
Shiva Chen 4891dbf557 [PATCH] [RISCV] Extend getTargetDefines for RISCVTargetInfo
Summary:
This patch extend getTargetDefines and implement handleTargetFeatures
and hasFeature. and define corresponding marco for those features.

Reviewers: asb, apazos, eli.friedman

Differential Revision: https://reviews.llvm.org/D44727

Patch by Kito Cheng.

llvm-svn: 329278
2018-04-05 12:54:00 +00:00
Richard Trieu b402580616 Fix some handling of AST nodes with diagnostics.
The diagnostic system for Clang can already handle many AST nodes.  Instead
of converting them to strings first, just hand the AST node directly to
the diagnostic system and let it handle the output.  Minor changes in some
diagnostic output.

llvm-svn: 328688
2018-03-28 04:16:13 +00:00
Hans Wennborg 1bbe00e0ca [ms] Parse #pragma optimize and ignore it behind its own flag
This allows users to turn off warnings about this pragma specifically,
while still receiving warnings about other ignored pragmas.

Differential Revision: https://reviews.llvm.org/D44630

llvm-svn: 327959
2018-03-20 08:53:11 +00:00
Sjoerd Meijer 50944d642e [AAch64] Tests for ACLE FP16 macros
This adds some missing tests for the AArch64 FP16 macros.

Differential Revision: https://reviews.llvm.org/D44512

llvm-svn: 327623
2018-03-15 13:36:30 +00:00
Sjoerd Meijer a7463df6e2 [ARM] ACLE FP16 feature test macros
This is a partial recommit of r327189 that was reverted
due to test issues. I.e., this recommits minimal functional
change, the FP16 feature test macros, and adds tests that 
were missing in the original commit.

llvm-svn: 327455
2018-03-13 22:11:06 +00:00
Matthew Voss 0a6a701f36 Correct the alignment for the PS4 target
https://reviews.llvm.org/D44218

llvm-svn: 326942
2018-03-07 20:48:16 +00:00
Mandeep Singh Grang ac24bb53bb [RISCV] Enable __int128_t and __uint128_t through clang flag
Summary:
If the flag -fforce-enable-int128 is passed, it will enable support for __int128_t and __uint128_t types.
This flag can then be used to build compiler-rt for RISCV32.

Reviewers: asb, kito-cheng, apazos, efriedma

Reviewed By: asb, efriedma

Subscribers: shiva0217, efriedma, jfb, dschuff, sdardis, sbc100, jgravelle-google, aheejin, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, cfe-commits

Differential Revision: https://reviews.llvm.org/D43105

llvm-svn: 326045
2018-02-25 03:58:23 +00:00
Craig Topper 94a940d2b4 [X86] Disable CLWB in Cannon Lake
Cannon Lake does not support CLWB, therefore it
does not include all features listed under SKX.

Patch by Gabor Buella

Differential Revision: https://reviews.llvm.org/D43459

llvm-svn: 325655
2018-02-21 00:16:50 +00:00
Keith Walker 167961f6dc [ARM] disable FPU features when using soft floating point.
To be compatible with GCC if soft floating point is in effect any FPU
specified is effectively ignored, eg,

  -mfloat-abi=soft -fpu=neon

If any floating point features which require FPU hardware are enabled
they must be disable.

There was some support for doing this for NEON, but it did not handle
VFP, nor did it prevent the backend from emitting the build attribute
Tag_FP_arch describing the generated code as using the floating point
hardware if a FPU was specified (even though soft float does not use
the FPU).

Disabling the hardware floating point features for targets which are
compiling for soft float has meant that some tests which were incorrectly
checking for hardware support also needed to be updated. In such cases,
where appropriate the tests have been updated to check compiling for
soft float and a non-soft float variant (usually softfp). This was
usually because the target specified in the test defaulted to soft float.

Differential Revision: https://reviews.llvm.org/D42569

llvm-svn: 325492
2018-02-19 12:40:26 +00:00
Saleem Abdulrasool fd4db5331e Support `#pragma comment(lib, "name")` in the frontend for ELF
This adds the frontend support required to support the use of the
comment pragma to enable auto linking on ELFish targets. This is a
generic ELF extension supported by LLVM. We need to change the handling
for the "dependentlib" in order to accommodate the previously discussed
encoding for the dependent library descriptor. Without the custom
handling of the PCK_Lib directive, the -l prefixed option would be
encoded into the resulting object (which is treated as a frontend
error).

llvm-svn: 324438
2018-02-07 01:46:46 +00:00
Walter Lee 637aafc451 [Myriad] Define __ma2x5x and __ma2x8x
Summary: Add architecture defines for ma2x5x and ma2x8x.

Reviewers: jyknight

Subscribers: fedor.sergeev, MartinO

Differential Revision: https://reviews.llvm.org/D42882

llvm-svn: 324420
2018-02-06 22:39:47 +00:00
Alex Bradbury 3e1478f866 [RISCV] Create a LinuxTargetInfo when targeting Linux
Previously, RISCV32TargetInfo or RISCV64TargetInfo were created 
unconditionally. Use LinuxTargetInfo<RISCV??TargetInfo> to ensure that the 
proper OS-specific defines are present.

This patch only adds logic to instantiate LinuxTargetInfo and leaves a TODO, 
as I'm reluctant to add logic for other targets (e.g. FreeBSD, RTEMS) until 
I've produced and tested at least one binary for that OS+target combo.

Thanks to @mgrang to reporting the issue.

llvm-svn: 324170
2018-02-03 11:56:11 +00:00
Craig Topper ace5c37c57 [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.
gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546

llvm-svn: 323552
2018-01-26 19:34:45 +00:00
Craig Topper 3672f00e01 [X86] Define __IBT__ when -mibt is specified.
llvm-svn: 323543
2018-01-26 18:31:14 +00:00
Craig Topper 8cdb94901d [X86] Add rdpid command line option and intrinsics.
Summary: This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made.

Reviewers: RKSimon, spatel, zvi, AndreiGrischenko

Reviewed By: RKSimon

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D42272

llvm-svn: 323047
2018-01-20 18:36:52 +00:00
Craig Topper c0b4aba786 [X86] Add missing check for RDSEED to ICL, CNL, SKX sections of test/Preprocessor/predefined-arch-macros.c
llvm-svn: 322912
2018-01-19 00:28:42 +00:00
Erich Keane cec95ec1a7 Revert 319303: Add _Float128 as alias to __float128 to enable compilations on Fedora27/glibc2
Differential Revision: https://reviews.llvm.org/D40673

llvm-svn: 322518
2018-01-15 21:16:25 +00:00
Alex Bradbury 71f45455e1 [RISCV] Add the RISCV target and compiler driver
As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver 
support (RV64 to follow).

Differential Revision: https://reviews.llvm.org/D39963

llvm-svn: 322276
2018-01-11 13:36:56 +00:00
Steven Wu b96a3a4fe5 Preserve unknown STDC pragma through preprocessor
Summary:
#pragma STDC FP_CONTRACT handler is only registered in parser so we
should keep the unknown STDC pragma through preprocessor and we also
should not emit warning for unknown STDC pragma during preprocessor.

rdar://problem/35724351

Reviewers: efriedma, rsmith, arphaman

Reviewed By: efriedma

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D41780

llvm-svn: 321909
2018-01-05 22:45:03 +00:00
Hubert Tong 7d96b79194 Use backslash escape, replacing xargs -0 in test macro-multiline.c
Summary:
xargs supports escaping of newline characters with backslash.
xargs -0 is neither part of POSIX nor the LSB.

This patch removes the -0 option and adjusts the input to xargs
accordingly; that is, the input is a text file not ending in an
incomplete line, and the newline of interest is preceded by a backslash.

Note: The treatment of escaped newline characters is not as clearly
specified by POSIX as for escaped blank characters; however, the same
can be said for escaped backslashes. It is slightly more clear for the
case where the -I option is used; however, -I is also of limited
portability.

Reviewers: bruno

Reviewed By: bruno

Subscribers: bruno, rcraik, cfe-commits

Differential Revision: https://reviews.llvm.org/D41544

llvm-svn: 321828
2018-01-04 22:58:30 +00:00
Craig Topper d2fe244a6a Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake."
I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Which specifically said CLWB wasn't until Icelake.

But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe.

I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing.

llvm-svn: 321547
2017-12-29 06:39:16 +00:00
Benjamin Kramer 3a13ed60ba Avoid int to string conversion in Twine or raw_ostream contexts.
Some output changes from uppercase hex to lowercase hex, no other functionality change intended.

llvm-svn: 321526
2017-12-28 16:58:54 +00:00
Craig Topper 520d055f66 [X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake.
We have cannonlake and icelake inheriting from skylake server in a switch using fallthroughs. But they aren't perfect supersets of skylake server.

llvm-svn: 321504
2017-12-27 22:26:01 +00:00
Craig Topper 5bd93e99e2 [X86] Test that -march=skx enables PKU.
llvm-svn: 321503
2017-12-27 22:26:00 +00:00
Craig Topper b36447d346 [X86] Enable avx512vpopcntdq and clwb for icelake.
Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference

llvm-svn: 321502
2017-12-27 22:25:59 +00:00
Coby Tayree a09663a5c1 [x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557

llvm-svn: 321487
2017-12-27 11:25:07 +00:00
Coby Tayree 3d9c88cfec [x86][icelake][vnni]
added vnni feature recognition
added intrinsics support for VNNI instructions
_mm256_mask_dpbusd_epi32
_mm256_maskz_dpbusd_epi32
_mm256_dpbusd_epi32
_mm256_mask_dpbusds_epi32
_mm256_maskz_dpbusds_epi32
_mm256_dpbusds_epi32
_mm256_mask_dpwssd_epi32
_mm256_maskz_dpwssd_epi32
_mm256_dpwssd_epi32
_mm256_mask_dpwssds_epi32
_mm256_maskz_dpwssds_epi32
_mm256_dpwssds_epi32
_mm128_mask_dpbusd_epi32
_mm128_maskz_dpbusd_epi32
_mm128_dpbusd_epi32
_mm128_mask_dpbusds_epi32
_mm128_maskz_dpbusds_epi32
_mm128_dpbusds_epi32
_mm128_mask_dpwssd_epi32
_mm128_maskz_dpwssd_epi32
_mm128_dpwssd_epi32
_mm128_mask_dpwssds_epi32
_mm128_maskz_dpwssds_epi32
_mm128_dpwssds_epi32
_mm512_mask_dpbusd_epi32
_mm512_maskz_dpbusd_epi32
_mm512_dpbusd_epi32
_mm512_mask_dpbusds_epi32
_mm512_maskz_dpbusds_epi32
_mm512_dpbusds_epi32
_mm512_mask_dpwssd_epi32
_mm512_maskz_dpwssd_epi32
_mm512_dpwssd_epi32
_mm512_mask_dpwssds_epi32
_mm512_maskz_dpwssds_epi32
_mm512_dpwssds_epi32
matching a similar work on the backend (D40208)
Differential Revision: https://reviews.llvm.org/D41558

llvm-svn: 321484
2017-12-27 10:37:51 +00:00
Coby Tayree 2268576fa0 [x86][icelake][bitalg]
added bitalg feature recognition
added intrinsics support for bitalg instructions
_mm512_popcnt_epi16
_mm512_mask_popcnt_epi16
_mm512_maskz_popcnt_epi16
_mm512_popcnt_epi8
_mm512_mask_popcnt_epi8
_mm512_maskz_popcnt_epi8
_mm512_mask_bitshuffle_epi64_mask
_mm512_bitshuffle_epi64_mask
_mm256_popcnt_epi16
_mm256_mask_popcnt_epi16
_mm256_maskz_popcnt_epi16
_mm128_popcnt_epi16
_mm128_mask_popcnt_epi16
_mm128_maskz_popcnt_epi16
_mm256_popcnt_epi8
_mm256_mask_popcnt_epi8
_mm256_maskz_popcnt_epi8
_mm128_popcnt_epi8
_mm128_mask_popcnt_epi8
_mm128_maskz_popcnt_epi8
_mm256_mask_bitshuffle_epi32_mask
_mm256_bitshuffle_epi32_mask
_mm128_mask_bitshuffle_epi16_mask
_mm128_bitshuffle_epi16_mask
matching a similar work on the backend (D40222)
Differential Revision: https://reviews.llvm.org/D41564

llvm-svn: 321483
2017-12-27 10:01:00 +00:00
Coby Tayree cf96c876c6 [x86][icelake][vpclmulqdq]
added vpclmulqdq feature recognition
added intrinsics support for vpclmulqdq instructions
  _mm256_clmulepi64_epi128
  _mm512_clmulepi64_epi128
matching a similar work on the backend (D40101)
Differential Revision: https://reviews.llvm.org/D41573

llvm-svn: 321480
2017-12-27 09:00:31 +00:00
Coby Tayree f4811ebc39 [x86][icelake][gfni]
added gfni feature recognition
added intrinsics support for gfni instructions
  _mm_gf2p8affineinv_epi64_epi8
  _mm_mask_gf2p8affineinv_epi64_epi8
  _mm_maskz_gf2p8affineinv_epi64_epi8
  _mm256_gf2p8affineinv_epi64_epi8
  _mm256_mask_gf2p8affineinv_epi64_epi8
  _mm256_maskz_gf2p8affineinv_epi64_epi8
  _mm512_gf2p8affineinv_epi64_epi8
  _mm512_mask_gf2p8affineinv_epi64_epi8
  _mm512_maskz_gf2p8affineinv_epi64_epi8
  _mm_gf2p8affine_epi64_epi8
  _mm_mask_gf2p8affine_epi64_epi8
  _mm_maskz_gf2p8affine_epi64_epi8
  _mm256_gf2p8affine_epi64_epi8
  _mm256_mask_gf2p8affine_epi64_epi8
  _mm256_maskz_gf2p8affine_epi64_epi8
  _mm512_gf2p8affine_epi64_epi8
  _mm512_mask_gf2p8affine_epi64_epi8
  _mm512_maskz_gf2p8affine_epi64_epi8
  _mm_gf2p8mul_epi8
  _mm_mask_gf2p8mul_epi8
  _mm_maskz_gf2p8mul_epi8
  _mm256_gf2p8mul_epi8
  _mm256_mask_gf2p8mul_epi8
  _mm256_maskz_gf2p8mul_epi8
  _mm512_gf2p8mul_epi8
  _mm512_mask_gf2p8mul_epi8
  _mm512_maskz_gf2p8mul_epi8
matching a similar work on the backend (D40373)
Differential Revision: https://reviews.llvm.org/D41582

llvm-svn: 321477
2017-12-27 08:37:47 +00:00
Coby Tayree a1e5f0c339 [x86][icelake][vaes]
added vaes feature recognition
added intrinsics support for vaes instructions, matching a similar work on the backend (D40078)
  _mm256_aesenc_epi128
  _mm512_aesenc_epi128
  _mm256_aesenclast_epi128
  _mm512_aesenclast_epi128
  _mm256_aesdec_epi128
  _mm512_aesdec_epi128
  _mm256_aesdeclast_epi128
  _mm512_aesdeclast_epi128

llvm-svn: 321474
2017-12-27 08:16:54 +00:00
Craig Topper 921aff6e90 [X86] Add missing check lines for the silvermont cases in predefined-arch-macros.c test.
llvm-svn: 321343
2017-12-22 05:09:38 +00:00
Craig Topper 66b110edce [X86] Add 'prfchw' to the correct CPUs to match the backend.
llvm-svn: 321341
2017-12-22 04:51:00 +00:00
Alex Lorenz 3b288c6e1b __is_target_environment: Check the environment after parsing it
This ensures that target triples with environment versions can still work with
__is_target_environment.

llvm-svn: 320854
2017-12-15 20:07:53 +00:00
Alex Lorenz 268759e58f __is_target_arch: Check the arch and subarch instead of the arch name
This ensures that when compiling for "arm64" __is_target_arch will succeed for
both "arm64" and "aarch64".

Thanks to Bob Wilson who pointed this out!

llvm-svn: 320853
2017-12-15 19:58:38 +00:00
Alex Lorenz 2cfa11a524 Commit missing tests for r320734
llvm-svn: 320735
2017-12-14 19:22:41 +00:00
Krzysztof Parzyszek cc5cd2c013 [Hexagon] Add front-end support for Hexagon V65
llvm-svn: 320579
2017-12-13 13:48:07 +00:00
Erich Keane 6c4835978a Revert 320391: Certain targets are failing, pulling back to diagnose.
llvm-svn: 320398
2017-12-11 18:14:51 +00:00
Erich Keane bb322555af For Linux/gnu compatibility, preinclude <stdc-predef.h> if the file is available
As reported in llvm bugzilla 32377.
Here’s a patch to add preinclude of stdc-predef.h.

The gcc documentation says “On GNU/Linux, <stdc-predef.h> is pre-included.” See https://gcc.gnu.org/gcc-4.8/porting_to.html;

The preinclude is inhibited with –ffreestanding.

Basically I fixed the failing test cases by adding –ffreestanding which inhibits this behavior.

I fixed all the failing tests, including some in extra/test, there's a separate patch for that which is linked here

Note: this is a recommit after a test failure took down the original (r318669)

Patch By: mibintc
Differential Revision: https://reviews.llvm.org/D34158

llvm-svn: 320391
2017-12-11 17:36:42 +00:00
Aaron Ballman 1c30924420 Add a test that the __STDC_VERSION__ macro reports the correct value for -std=c17.
llvm-svn: 320131
2017-12-08 02:39:26 +00:00
Aaron Ballman 7c18159bb5 Correct line endings that got mixed up in r320088; NFC.
llvm-svn: 320115
2017-12-07 23:10:09 +00:00
Aaron Ballman 48f5f4d895 Add support for the __has_c_attribute builtin preprocessor macro.
This behaves similar to the __has_cpp_attribute builtin macro in that it allows users to detect whether an attribute is supported with the [[]] spelling syntax, which can be enabled in C with -fdouble-square-bracket-attributes.

llvm-svn: 320088
2017-12-07 21:37:49 +00:00
Taewook Oh cebac48bf7 Stringizing raw string literals containing newline
Summary: This patch implements 4.3 of http://open-std.org/jtc1/sc22/wg21/docs/papers/2014/n4220.pdf. If a raw string contains a newline character, replace each newline character with the \n escape code. Without this patch, included test case (macro_raw_string.cpp) results compilation failure.

Reviewers: rsmith, doug.gregor, jkorous-apple

Reviewed By: jkorous-apple

Subscribers: jkorous-apple, vsapsai, cfe-commits

Differential Revision: https://reviews.llvm.org/D39279

llvm-svn: 319904
2017-12-06 17:00:53 +00:00
Ed Schouten 1382a32a73 Add __WINT_MAX__.
This definition is similar to __WCHAR_MAX__, except that it applies to
wint_t. It's also documented as being supported by GCC 4.5 and later.

llvm-svn: 319746
2017-12-05 09:13:18 +00:00
Erich Keane 45cf85b415 Add _Float128 as alias to __float128 to enable compilations on Fedora27/glibc2-26
Fedora27 is using a new version of glibc that refers to the _Float128 type. This
patch adds that name as an alias to float128. I also added some predefined macro
values for the digits, mantissa, epilon, etc (FloatMacros). For the test case, I
copied an existing float128 test. This functionality needs work long term, but 
it should be sufficient to tread water for a while. At Intel we have test
servers running our LLVM compiler with various open source workloads, the server
has been upgraded to Fedora27 so many workloads are failing due to _Float128.

Patch-By: mibintc
Differential Revision: https://reviews.llvm.org/D40673

llvm-svn: 319703
2017-12-04 21:58:43 +00:00
Sven van Haastregt d141e4806b [OpenCL] Define __IMAGE_SUPPORT__ macro for SPIR
Add #define __IMAGE_SUPPORT__ 1 for SPIR targets to indicate that SPIR
supports images.

Patch by Dmitry Borisenkov.

Differential Revision: https://reviews.llvm.org/D40252

llvm-svn: 319658
2017-12-04 15:01:08 +00:00
Keith Walker c5bbd11406 Revert [ARM] disable FPU features when using soft floating point.
This reverts r319420
It is failing the test Driver/arm-mfpu.c so reverting while I investigate the failure.

llvm-svn: 319425
2017-11-30 12:05:18 +00:00