3 Commits

Author	SHA1	Message	Date
Hsiangkai Wang	6e360460f1	[RISCV] Use v8-v23 as argument registers to conform to the proposal. ... The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Fraser Cormack	cf8f682c2d	[RISCV] Adjust tested vor ops for more stable tests. NFC.	2020-12-28 19:33:25 +00:00
Fraser Cormack	1a7ac29a89	[RISCV] Add ISel support for RVV vector/scalar forms ... This patch extends the SDNode ISel support for RVV from only the vector/vector instructions to include the vector/scalar and vector/immediate forms. It uses splat_vector to carry the scalar in each case, except when XLEN<SEW (RV32 SEW=64) when a custom node `SPLAT_VECTOR_I64` is used for type-legalization and to encode the fact that the value is sign-extended to SEW. When the scalar is a full 64-bit value we use a sequence to materialize the constant into the vector register. The non-intrinsic ISel patterns have also been split into their own file. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Fraser Cormack <fraser@codeplay.com> Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D93312	2020-12-23 20:16:18 +00:00