Commit Graph

355817 Commits

Author SHA1 Message Date
Igor Kudrin 2a7af30482 [DebugInfo] Separate fields with commas in headers of compile units (2/3).
For most tables, we already use commas in headers. This set of patches
unifies dumping the remaining ones.

Differential Revision: https://reviews.llvm.org/D80806
2020-06-01 17:40:24 +07:00
Igor Kudrin 937403d684 [DebugInfo] Separate fields with commas in headers of .debug_pub* tables (1/3).
For most tables, we already use commas in headers. This set of patches
unifies dumping the remaining ones.

Differential Revision: https://reviews.llvm.org/D80806
2020-06-01 17:39:48 +07:00
Georgii Rymar b21f32fcec [llvm-readelf] - Add explicit braces again. NFC.
Partially reverts feee98645d.

Add explicit braces to a different place to fix
"error: add explicit braces to avoid dangling else [-Werror,-Wdangling-else]"
2020-06-01 13:10:16 +03:00
Georgii Rymar feee98645d [llvm-readelf] - Add explicit braces. NFC.
Should fix the BB (http://lab.llvm.org:8011/builders/clang-ppc64le-rhel/builds/3907/steps/build%20stage%201/logs/stdio):

llvm-readobj/ELFDumper.cpp:4708:5: error: add explicit braces to avoid dangling else [-Werror,-Wdangling-else]
    else
    ^
2020-06-01 12:55:24 +03:00
Ehud Katz 85c3088049 [StructurizeCFG] Fix region nodes ordering
This is a reimplementation of the `orderNodes` function, as the old
implementation didn't take into account all cases.
The new implementation uses SCCs instead of Loops to take account of
irreducible loops.

Fix PR41509

Differential Revision: https://reviews.llvm.org/D79037
2020-06-01 12:50:35 +03:00
Georgii Rymar e75efcc3c1 [llvm-readobj] - Improve error reporting for hash tables.
This improves the next points for broken hash tables:

1) Use reportUniqueWarning to prevent duplication when
   --hash-table and --elf-hash-histogram are used together.

2) Dump nbuckets and nchain fields. It is often possible
   to dump them even when the table itself goes past the EOF etc.

Differential revision: https://reviews.llvm.org/D80373
2020-06-01 12:36:23 +03:00
Tim Northover dace8224f3 AArch64: materialize large stack offset into xzr correctly.
When a stack offset was too big to materialize in a single instruction, we were
trying to do it in stages:

    adds xD, sp, #imm
    adds xD, xD, #imm

Unfortunately, if xD is xzr then the second instruction doesn't exist and
wouldn't do what was needed if it did. Instead we can use a temporary register
for all but the last addition.
2020-06-01 09:30:05 +01:00
Djordje Todorovic 40a3fcb05c [DebugInfo][CallSites] Remove decl subprograms from 'retainedTypes:'
After the D70350, the retainedTypes: isn't being used for the purpose
of call site debug info for extern calls, so it is safe to delete it
from IR representation.
We are also adding a test to ensure the subprogram isn't stored within
the retainedTypes: from corresponding DICompileUnit.

Differential Revision: https://reviews.llvm.org/D80369
2020-06-01 09:10:05 +02:00
Nathan James b6d23f2efc [ASTMatchers] Force c++ unittests to specify correct language standard
Force the unittests on c++ code for matchers to specify the correct standard.

Reviewed By: gribozavr2

Differential Revision: https://reviews.llvm.org/D80884
2020-06-01 07:52:01 +01:00
serge-sans-paille 11efb0837c Improve SmallPtrSetImpl::count implementation
Relying on the find method implies a roundtrip to the iterator world, which is
not costless because iterator creation involves a few check to ensure the
iterator is in a valid position (through the SmallPtrSetIteratorImpl::AdvanceIfNotValid
method). It turns out that the result of SmallPtrSetImpl::find_imp is either
valid or the EndPointer, so there's no need to go through that abstraction,
and the compiler cannot guess it.

Differential Revision: https://reviews.llvm.org/D80708
2020-06-01 07:49:19 +02:00
serge-sans-paille af38074874 Fix strict aliasing warning in msan.cpp
Use internal_memcpy instead.

Differential Revision: https://reviews.llvm.org/D80732
2020-06-01 07:42:10 +02:00
Chen Zheng 2a24d350db [MachineCombine] add a hook for resource length limit 2020-05-31 23:21:04 -04:00
Li Rong Yi 3101601b54 [PowerPC] Exploit vabsd on P9
Summary: Exploit vabsd* for for absolute difference of vectors on P9,
for example:
void foo (char *restrict p, char *restrict q, char *restrict t)
{
  for (int i = 0; i < 16; i++)
     t[i] = abs (p[i] - q[i]);
}
this case should be matched to the HW instruction vabsdub.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D80271
2020-06-01 02:30:27 +00:00
Nico Weber 216bad9a64 [gn build] (semi-manually) port a8ca0ec267 2020-05-31 22:06:11 -04:00
Matt Arsenault a8ca0ec267 AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass 2020-05-31 20:40:14 -04:00
Fangrui Song 92448fd23d [Driver] Simplify Linux::addProfileRTLibs 2020-05-31 17:15:14 -07:00
Kirstóf Umann 77e1181df4 [analyzer] Add dumps to CheckerRegistry 2020-05-31 22:53:02 +02:00
Hubert Tong c15d5d12c6 [Driver] NFC: Use Twine temp to replace std::string local
This patch replaces a `std::string` local used for a concatentation with
a `Twine` where the string was being passed into call.
2020-05-31 16:38:10 -04:00
Hubert Tong 403d5a5e35 [test][compiler-rt] Avoid LD_PRELOAD for "outer" dynamic linkers
Summary:
This patch moves the setting of `LD_PRELOAD` "inwards" to avoid issues
where the built library needs to be loaded with the dynamic linker that
was configured with the build (and cannot, for example, be loaded by the
dynamic linker associated with the `env` utility).

Reviewed By: vitalybuka, nemanjai, jsji

Differential Revision: https://reviews.llvm.org/D79695
2020-05-31 16:33:42 -04:00
Craig Topper 8abe830093 [X86] Rewrite how X86PartialReduction finds candidates to consider optimizing.
Previously we walked the users of any vector binop looking for
more binops with the same opcode or phis that eventually ended up
in a reduction. While this is simple it also means visiting the
same nodes many times since we'll do a forward walk for each
BinaryOperator in the chain. It was also far more general than what
we have tests for or expect to see.

This patch replaces the algorithm with a new method that starts at
extract elements looking for a horizontal reduction. Once we find
a reduction we walk through backwards through phis and adds to
collect leaves that we can consider for rewriting.

We only consider single use adds and phis. Except for a special
case if the Add is used by a phi that forms a loop back to the
Add. Including other single use Adds to support unrolled loops.

Ultimately, I want to narrow the Adds, Phis, and final reduction
based on the partial reduction we're doing. I still haven't
figured out exactly what that looks like yet. But restricting
the types of graphs we expect to handle seemed like a good first
step. As does having all the leaves and the reduction at once.

Differential Revision: https://reviews.llvm.org/D79971
2020-05-31 12:53:01 -07:00
Simon Pilgrim 22e50833e9 [X86][AVX] Reduce unary target shuffles width if the upper elements aren't demanded. 2020-05-31 20:19:24 +01:00
Simon Pilgrim 8f2f613a6e [X86][AVX] combineX86ShufflesRecursively - peekThroughOneUseBitcasts subvector before widening.
This matches what we do for the full sized vector ops at the start of combineX86ShufflesRecursively, and helps getFauxShuffleMask extract more INSERT_SUBVECTOR patterns.
2020-05-31 19:58:33 +01:00
Chris Lattner 0cf5ef176b Change some extraneous /// comments to // comments inside methods. NFC. 2020-05-31 11:43:54 -07:00
Nathan James 5952125691 clang-tidy and clang-query wont crash with invalid command line options
Motivated by [[ https://bugs.llvm.org/show_bug.cgi?id=46141 | clang-tidy crashed for unknown command line argument. ]]

Reviewed By: aaron.ballman, thakis

Differential Revision: https://reviews.llvm.org/D80879
2020-05-31 17:41:29 +01:00
Nathan James f4b0ebb89b Revert "clang-tidy and clang-query wont crash with invalid command line options"
This reverts commit f23ddbe3c3.
2020-05-31 16:40:09 +01:00
Sanjay Patel dfbfdc96f9 [utils] update expected strings in tests; NFC
The script was changes with:
bfdc255266
2020-05-31 11:07:22 -04:00
Nathan James f23ddbe3c3 clang-tidy and clang-query wont crash with invalid command line options
Summary: Motivated by [[ https://bugs.llvm.org/show_bug.cgi?id=46141 | clang-tidy crashed for unknown command line argument. ]]

Reviewers: aaron.ballman, alexfh

Reviewed By: aaron.ballman

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D80879
2020-05-31 16:01:41 +01:00
Matt Arsenault 95f65a7c6c AArch64/GlobalISel: Fix incorrect ptrmask usage for alignment
I inverted the mask when I ported to the new form of G_PTRMASK in
8bc03d2168.

I don't think this really broke anything, since G_VASTART isn't
handled for types with an alignment higher than the stack alignment.
2020-05-31 10:56:55 -04:00
Sanjay Patel bfdc255266 [utils] change update_test_checks.py use of 'TMP' value names
As discussed in PR45951:
https://bugs.llvm.org/show_bug.cgi?id=45951

There's a potential name collision between update_test_checks.py and -instnamer
and/or manually-generated IR test files because all of them try to use the
variable name that should never be used: "tmp".

This patch proposes to reduce the odds of collision and adds a warning if we
detect the problem. This will cause regression test churn when regenerating
CHECK lines on existing files.

Differential Revision: https://reviews.llvm.org/D80584
2020-05-31 10:46:11 -04:00
Sanjay Patel 91b45fb527 [PhaseOrdering] add test for hoisting/CSE (PR46115); NFC 2020-05-31 10:34:18 -04:00
Simon Pilgrim 4a2673d79f [X86][AVX] Add SimplifyMultipleUseDemandedBits VBROADCAST handling to SimplifyDemandedVectorElts.
As suggested on D79987.
2020-05-31 14:20:15 +01:00
Sanjay Patel e31f2a894a [VectorCombine] add tests for scalarizing binop-with-constant; NFC
Goes with proposal in D80885.

This is adapted from the InstCombine tests that were added for
D50992

But these should be adjusted further to provide more interesting
scenarios for x86-specific codegen. Eg, vector types/sizes will
have different costs depending on ISA attributes.

We also need to add tests that include a load of the scalar
variable and add tests that include extra uses of the insert
to further exercise the cost model.
2020-05-31 09:11:30 -04:00
Simon Pilgrim f046326847 [X86] getFauxShuffleMask/getTargetShuffleInputs - make SelectionDAG const (PR45974).
Try to prevent future node creation issues (as detailed in PR45974) by making the SelectionDAG reference const, so it can still be used for analysis, but not node creation.
2020-05-31 13:51:01 +01:00
Simon Pilgrim 15b281d780 [X86][AVX] Add test case described in D79987 2020-05-31 13:51:00 +01:00
Sanjay Patel 129c501aa9 [PhaseOrdering] add scalarization test for PR42174; NFC
Motivating test for vector-combine enhancement in D80885.
Make sure that vectorization and canonicalization are
working together as expected.
2020-05-31 08:43:34 -04:00
Simon Pilgrim d33ba1aa0b [X86][AVX] getFauxShuffleMask - don't widen shuffle inputs from INSERT_SUBVECTOR(X,SHUFFLE(Y,Z))
Don't create nodes on the fly when decoding INSERT_SUBVECTOR as faux shuffles.
2020-05-31 13:19:18 +01:00
Simon Pilgrim 45ebe38ffc [X86][AVX] Pad small shuffle inputs in combineX86ShufflesRecursively
As detailed on PR45974 and D79987, getFauxShuffleMask is creating nodes on the fly to create shuffles with inputs the same size as the result, causing problems for hasOneUse() checks in later simplification stages.

Currently only combineX86ShufflesRecursively benefits from these widened inputs so I've begun moving the functionality there, and out of getFauxShuffleMask. This allows us to remove the widening from VBROADCAST and *EXTEND* faux shuffle cases.

This just leaves the INSERT_SUBVECTOR case in getFauxShuffleMask still creating nodes, which will require more extensive refactoring.
2020-05-31 11:43:47 +01:00
Florian Hahn ec25a71eb7 [ScheduleDAG] Avoid unnecessary recomputation of topological order.
In some cases ScheduleDAGRRList has to add new nodes to resolve problems
with interfering physical registers. When new nodes are added, it
completely re-computes the topological order, which can take a long
time, but is unnecessary. We only add nodes one by one, and initially
they do not have any predecessors. So we can just insert them at the end
of the vector. Later we add predecessors, but the helper function
properly updates the topological order much more efficiently. With this
change, the compile time for the program below drops from 300s to 30s on
my machine.

    define i11129 @test1() {
      %L1 = load i11129, i11129* undef
      %B30 = ashr i11129 %L1, %L1
      store i11129 %B30, i11129* undef
      ret i11129 %L1
    }

This should be generally beneficial, as we can skip a large amount of
work. Theoretically there are some scenarios where we might not safe
much, e.g. when we add a dependency between the first and last node.
Then we would have to shift all nodes. But we still do not have to spend
the time re-computing the initial order.

Reviewers: MatzeB, atrick, efriedma, niravd, paquette

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D59722
2020-05-31 11:04:35 +01:00
Kang Zhang bfdf9ef009 Revert "[NFC][PowerPC] Add a new case to test phi-node-elimination pass"
This case wll be failed on some machines which enable expensive-checks.

This reverts commit af3abbf7bd.
2020-05-31 09:24:21 +00:00
Kang Zhang af3abbf7bd [NFC][PowerPC] Add a new case to test phi-node-elimination pass 2020-05-31 08:05:27 +00:00
Jay Foad 2768edfff1 [AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS
Differential Revision: https://reviews.llvm.org/D80813
2020-05-31 05:21:55 +01:00
Jay Foad d4751f3556 [AMDGPU] Precommit tests for D80813 2020-05-31 05:21:55 +01:00
Changpeng Fang 234eba90f4 AMDGPU: Add setTruncStoreAction for vector i64 types made legal recently
Reviewers:
  rampitec, arsenm

Differential Revision:
  https://reviews.llvm.org/D80853
2020-05-30 20:45:27 -07:00
Craig Topper dbda87186e [X86] Remove unneeded bitconverts from isel patterns. NFC
The types already match so TableGen is removing the bitconvert.
2020-05-30 20:24:52 -07:00
Craig Topper 7c3b8077cc [X86] Add DAG combine to turn (v2i64 (scalar_to_vector (i64 (bitconvert (mmx))))) to MOVQ2DQ. Remove unneeded isel patterns.
We already had a DAG combine for (mmx (bitconvert (i64 (extractelement v2i64))))
to MOVDQ2Q.

Remove patterns for MMX_MOVQ2DQrr/MMX_MOVDQ2Qrr that use
scalar_to_vector/extractelement involving i64 scalar type with
v2i64 and x86mmx.
2020-05-30 19:47:08 -07:00
Craig Topper a4dd45b7d0 [DAGCombiner] Move debug message and statistic update into CommitTargetLoweringOpt.
This code was repeated in two callers of CommitTargetLoweringOpt.
But CommitTargetLoweringOpt is also called from TargetLowering.
We should print a message for those calls to. So sink the
repeated code into CommitTargetLoweringOpt to catch those calls.
2020-05-30 19:47:07 -07:00
Craig Topper af1accdd86 [X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero. 2020-05-30 19:47:07 -07:00
Craig Topper 1ecf39d607 [X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64.
The type profile and isel pattern have this type declared as
being MVT::v2i64. But isel skips the explicit type check due to
the type profile.
2020-05-30 19:47:07 -07:00
Craig Topper efc5857b0b [X86] Autogenerate complete checks. NFC 2020-05-30 19:47:07 -07:00
Craig Topper 8857822452 [X86] Move MMX_SET0 pattern into the instruction definition. NFC 2020-05-30 19:47:07 -07:00