Commit Graph

185 Commits

Author SHA1 Message Date
Greg Clayton 34132754bd Fixed some issues with ARM backtraces by not processing any push/pop
instructions if they are conditional. Also fixed issues where the PC wasn't
getting bit zero stripped for ARM targets when a stack frame was thumb. We
now properly call through the GetOpcodeLoadAddress() functions to make sure
the addresses are properly stripped for any targets that may decorate up
their addresses.

We now don't pass the SIGSTOP signals along. We can revisit this soon, but
currently this was interfering with debugging some older ARM targets that
don't have vCont support in the GDB server.

llvm-svn: 134461
2011-07-06 04:07:21 +00:00
Johnny Chen b1fa6b466b Bail out if we have an invalid thumb instruction.
llvm-svn: 132511
2011-06-02 23:19:06 +00:00
Johnny Chen 8a71c0b771 Turn the commented-out assert()'s into appropriate bail-out actions.
llvm-svn: 132507
2011-06-02 23:07:03 +00:00
Johnny Chen 6ef2735631 When emulating an ill-formed instruction, we should bail out instead of asserting and bringing down the whole process.
llvm-svn: 132506
2011-06-02 22:50:51 +00:00
Greg Clayton 850cc8998c Remove asserts that will crash LLDB. These should be changed to return
true/false in an extra boolean parameter and not cause the the binary that
us using the LLDB framework to crash.

llvm-svn: 132501
2011-06-02 22:23:35 +00:00
Johnny Chen 8a742f5f37 EmulateShiftReg() also accepts shifter type of SRType_ROR.
llvm-svn: 132484
2011-06-02 21:00:34 +00:00
Greg Clayton 8d400e1750 Fixed an issue in the EmulateInstructionARM there the IT opcode was trying to
parse NOP instructions. I added the new table entries for the NOP for the
plain NOP, Yield, WFE, WFI, and SEV variants. Modified the opcode emulation
function EmulateInstructionARM::EmulateMOVRdSP(...) to notify us when it is
creating a frame. Also added an abtract way to detect the frame pointer 
register for both the standard ARM ABI and for Darwin.

Fixed GDBRemoteRegisterContext::WriteAllRegisterValues(...) to correctly be
able to individually write register values back if case the 'G' packet is
not implemented or returns an error.

Modified the StopInfoMachException to "trace" stop reasons. On ARM we currently
use the BVR/BCR register pairs to say "stop when the PC is not equal to the 
current PC value", and this results in a EXC_BREAKPOINT mach exception that
has 0x102 in the code.

Modified debugserver to create the short option string from long option
definitions to make sure it doesn't get out of date. The short option string
was missing many of the newer short option values due to a modification of
the long options defs, and not modifying the short option string.

llvm-svn: 131911
2011-05-23 18:04:09 +00:00
Greg Clayton cd482e359e Added a way to resolve an load address from a target:
bool
Address::SetLoadAddress (lldb::addr_t load_addr, Target *target);

Added an == and != operator to RegisterValue.

Modified the ThreadPlanTracer to use RegisterValue objects to store the
register values when single stepping. Also modified the output to be a bit
less wide.

Fixed the ABIMacOSX_arm to not overwrite stuff on the stack. Also made the
trivial function call be able to set the ARM/Thumbness of the target 
correctly, and also sets the return value ARM/Thumbness.

Fixed the encoding on the arm s0-s31 and d16 - d31 registers when the default
register set from a standard GDB server register sets.

llvm-svn: 131517
2011-05-18 01:58:14 +00:00
Greg Clayton 31f1d2f535 Moved all code from ArchDefaultUnwindPlan and ArchVolatileRegs into their
respective ABI plugins as they were plug-ins that supplied ABI specfic info.

Also hookep up the UnwindAssemblyInstEmulation so that it can generate the
unwind plans for ARM.

Changed the way ABI plug-ins are handed out when you get an instance from
the plug-in manager. They used to return pointers that would be mananged
individually by each client that requested them, but now they are handed out
as shared pointers since there is no state in the ABI objects, they can be
shared.

llvm-svn: 131193
2011-05-11 18:39:18 +00:00
Greg Clayton 7349bd9078 While implementing unwind information using UnwindAssemblyInstEmulation I ran
into some cleanup I have been wanting to do when reading/writing registers.
Previously all RegisterContext subclasses would need to implement:

virtual bool
ReadRegisterBytes (uint32_t reg, DataExtractor &data);

virtual bool
WriteRegisterBytes (uint32_t reg, DataExtractor &data, uint32_t data_offset = 0);

There is now a new class specifically designed to hold register values: 
        lldb_private::RegisterValue
        
The new register context calls that subclasses must implement are:

virtual bool
ReadRegister (const RegisterInfo *reg_info, RegisterValue &reg_value) = 0;

virtual bool
WriteRegister (const RegisterInfo *reg_info, const RegisterValue &reg_value) = 0;

The RegisterValue class must be big enough to handle any register value. The
class contains an enumeration for the value type, and then a union for the 
data value. Any integer/float values are stored directly in an appropriate
host integer/float. Anything bigger is stored in a byte buffer that has a length
and byte order. The RegisterValue class also knows how to copy register value
bytes into in a buffer with a specified byte order which can be used to write
the register value down into memory, and this does the right thing when not
all bytes from the register values are needed (getting a uint8 from a uint32
register value..). 

All RegiterContext and other sources have been switched over to using the new
regiter value class.

llvm-svn: 131096
2011-05-09 20:18:18 +00:00
Greg Clayton e5b3498eef Added the start of the CFI row production using the
emulate instruction classes.

llvm-svn: 130556
2011-04-29 22:50:31 +00:00
Greg Clayton 84c39663a9 Added a new OptionValue subclass for lldb::Format: OptionValueFormat. Added
new OptionGroup subclasses for:
- output file for use with options: 
        long opts: --outfile <path> --append--output
        short opts: -o <path> -A
        
- format for use with options:
        long opts: --format <format>

- variable object display controls for depth, pointer depth, wether to show
  types, show summary, show location, flat output, use objc "po" style summary.
  
Modified ValueObjectMemory to be able to be created either with a TypeSP or
a ClangASTType.

Switched "memory read" over to use OptionGroup subclasses: one for the outfile
options, one for the command specific options, and one for the format.

llvm-svn: 130334
2011-04-27 22:04:39 +00:00
Greg Clayton 79ea878bf9 Got the EmulateInstruction CFI code a lot closer to producing CFI data.
Switch the EmulateInstruction to use the standard RegisterInfo structure
that is defined in the lldb private types intead of passing the reg kind and
reg num everywhere. EmulateInstruction subclasses also need to provide
RegisterInfo structs given a reg kind and reg num. This eliminates the need
for the GetRegisterName() virtual function and allows more complete information
to be passed around in the read/write register callbacks. Subclasses should
always provide RegiterInfo structs with the generic register info filled in as
well as at least one kind of register number in the RegisterInfo.kinds[] array.

llvm-svn: 130256
2011-04-26 23:48:45 +00:00
Johnny Chen a85bf380ba Modify EmulateInstructionARM::SetArchitecture() to treat "arm" and "thumb" as wild card architectures
for now, in order to fix the test failure for the 'arm_emulation' directory.
There might be a better way.

llvm-svn: 130227
2011-04-26 18:51:57 +00:00
Greg Clayton 2ed751bd47 Changed the emulate instruction function to take emulate options which
are defined as enumerations. Current bits include:

        eEmulateInstructionOptionAutoAdvancePC
        eEmulateInstructionOptionIgnoreConditions

Modified the EmulateInstruction class to have a few more pure virtuals that
can help clients understand how many instructions the emulator can handle:

        virtual bool
        SupportsEmulatingIntructionsOfType (InstructionType inst_type) = 0;


Where instruction types are defined as:

//------------------------------------------------------------------
/// Instruction types
//------------------------------------------------------------------    
typedef enum InstructionType
{
    eInstructionTypeAny,                // Support for any instructions at all (at least one)
    eInstructionTypePrologueEpilogue,   // All prologue and epilogue instructons that push and pop register values and modify sp/fp
    eInstructionTypePCModifying,        // Any instruction that modifies the program counter/instruction pointer
    eInstructionTypeAll                 // All instructions of any kind

}  InstructionType;


This allows use to tell what an emulator can do and also allows us to request
these abilities when we are finding the plug-in interface.

Added the ability for an EmulateInstruction class to get the register names
for any registers that are part of the emulation. This helps with being able
to dump and log effectively.

The UnwindAssembly class now stores the architecture it was created with in
case it is needed later in the unwinding process.

Added a function that can tell us DWARF register names for ARM that goes
along with the source/Utility/ARM_DWARF_Registers.h file: 

        source/Utility/ARM_DWARF_Registers.c
        
Took some of plug-ins out of the lldb_private namespace.

llvm-svn: 130189
2011-04-26 04:39:08 +00:00
Caroline Tice de2fb9cf76 Change code for reading emulation data files to read the new file
format.  (The newly formatted files will go in as a separate commit in a
few minutes).

llvm-svn: 129981
2011-04-22 05:08:45 +00:00
Caroline Tice 3ac6711aec Add the infrastructure to test instruction emulations automatically.
The idea is that the instruction to be emulated is actually executed
on the hardware to be emulated, with the before and after state of the
hardware being captured and 'freeze-dried' into .dat files.  The
emulation testing code then loads the before & after state from the
.dat file, emulates the instruction using the before state, and
compares the resulting state to the 'after' state.  If they match, the
emulation is accurate, otherwise there is a problem.

The final format of the .dat files needs a bit more work; the plan is
to generalize them a bit and to convert the plain values to key-value pairs. 
But I wanted to get this first pass committed.

This commit adds arm instruction emulation testing to the testsuite, along with
many initial .dat files.

It also fixes a bug in the llvm disassembler, where 32-bit thumb opcodes
were getting their upper & lower 16-bits reversed.

There is a new Instruction sub-class, that is intended to be loaded
from a .dat file rather than read from an executable.  There is also a
new EmulationStateARM class, for handling the before & after states.
EmulationStates for other architetures can be added later when we
emulate their instructions.

llvm-svn: 129832
2011-04-19 23:30:03 +00:00
Caroline Tice 17f5fa2b1c Fix bug where source & target registers were swapped in an
emulation function.

llvm-svn: 129474
2011-04-13 21:49:04 +00:00
Caroline Tice 69955f6cdc Fix various minor bugs in the ARM instruction emulation code.
llvm-svn: 129422
2011-04-13 00:42:12 +00:00
Caroline Tice 88544c5f2c Implement ARM emulation function to handle "SUBS PC, LR and related instructions".
llvm-svn: 129279
2011-04-11 15:51:10 +00:00
Caroline Tice 25d61ac2ed Fix various things in the instruction emulation code:
- Add ability to control whether or not the emulator advances the
    PC register (in the emulation state), if the instruction itself
    does not change the pc value..

    - Fix a few typos in asm description strings.

    - Fix bug in the carry flag calculation.

llvm-svn: 129168
2011-04-08 23:33:06 +00:00
Stephen Wilson 05459c8269 Add the ARM instruction emulation makefile.
I forgot to 'svn add' this file in r129119.

llvm-svn: 129120
2011-04-08 02:11:29 +00:00
Caroline Tice 7c9dd3ce3c Add Emulate and DumpEmulation to Instruction class.
Move InstructionLLVM out of DisassemblerLLVM class.

Add instruction emulation function calls to SBInstruction and SBInstructionList APIs.

llvm-svn: 128956
2011-04-05 23:22:54 +00:00
Caroline Tice ad379efc86 Add the rest of the mechanisms to make ARM instruction emulation usable/possible.
llvm-svn: 128907
2011-04-05 18:46:00 +00:00
Caroline Tice d20c8d1a17 Fix a few typos in the previous commit.
llvm-svn: 128671
2011-03-31 21:31:50 +00:00
Caroline Tice 028b8b7bb7 Add code to emulate VLD1 (single element to all lanes) ARM instruction.
llvm-svn: 128669
2011-03-31 21:15:29 +00:00
Caroline Tice 5901ea7e67 Add code to emulate VST1 (single element from one lane) ARM
instruction (more floating point stores).

llvm-svn: 128661
2011-03-31 19:17:12 +00:00
Caroline Tice d64a08144c Add code to emulate VST1 (multiple single elements) ARM
instruction (floating point store).

llvm-svn: 128656
2011-03-31 18:44:04 +00:00
Caroline Tice bc2b96b699 Add code to emulate VLD1 (single element to one lane) floating point
register load instruction (ARM) .

llvm-svn: 128646
2011-03-31 17:58:23 +00:00
Caroline Tice 31d8498f6f Add code to emulate VLD1 (multiple single elements) ARM instruction.
llvm-svn: 128637
2011-03-31 16:41:19 +00:00
Caroline Tice 8e4ed85520 Add code to emulate VSTR ARM instruction (store a floating point register).
llvm-svn: 128614
2011-03-31 05:38:36 +00:00
Caroline Tice df6dec754b Add code to emulate the VLDR Arm instruction (load a floating poitn register).
llvm-svn: 128613
2011-03-31 05:05:30 +00:00
Caroline Tice b5c6a3e50a Add "Bits64" utility function.
Add code to emulate VSTM ARM instruction (store multiple floating point registers).

llvm-svn: 128609
2011-03-31 03:26:23 +00:00
Caroline Tice 920c6c9855 Modify ARM instruction tables to allow for specifying floating point variants.
Add code to emulate VLDM ARM instruction (loading multiplt floating point registers).

Add function declarations for other floating point instructions to emulate.

llvm-svn: 128589
2011-03-31 00:02:51 +00:00
Caroline Tice 55bff33b50 Fill in code for EmulateSTRDImm and EmulateSTRDReg, to emulate the
STRD (immediate) and STRD (register) instructions.

llvm-svn: 128570
2011-03-30 19:02:56 +00:00
Greg Clayton 32e0a7509c Many improvements to the Platform base class and subclasses. The base Platform
class now implements the Host functionality for a lot of things that make 
sense by default so that subclasses can check:

int
PlatformSubclass::Foo ()
{
    if (IsHost())
        return Platform::Foo (); // Let the platform base class do the host specific stuff
    
    // Platform subclass specific code...
    int result = ...
    return result;
}

Added new functions to the platform:

    virtual const char *Platform::GetUserName (uint32_t uid);
    virtual const char *Platform::GetGroupName (uint32_t gid);

The user and group names are cached locally so that remote platforms can avoid
sending packets multiple times to resolve this information.

Added the parent process ID to the ProcessInfo class. 

Added a new ProcessInfoMatch class which helps us to match processes up
and changed the Host layer over to using this new class. The new class allows
us to search for processs:
1 - by name (equal to, starts with, ends with, contains, and regex)
2 - by pid
3 - And further check for parent pid == value, uid == value, gid == value, 
    euid == value, egid == value, arch == value, parent == value.
    
This is all hookup up to the "platform process list" command which required
adding dumping routines to dump process information. If the Host class 
implements the process lookup routines, you can now lists processes on 
your local machine:

machine1.foo.com % lldb
(lldb) platform process list 
PID    PARENT USER       GROUP      EFF USER   EFF GROUP  TRIPLE                   NAME
====== ====== ========== ========== ========== ========== ======================== ============================
99538  1      username   usergroup  username   usergroup  x86_64-apple-darwin      FileMerge
94943  1      username   usergroup  username   usergroup  x86_64-apple-darwin      mdworker
94852  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Safari
94727  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Xcode
92742  92710  username   usergroup  username   usergroup  i386-apple-darwin        debugserver


This of course also works remotely with the lldb-platform:

machine1.foo.com % lldb-platform --listen 1234

machine2.foo.com % lldb
(lldb) platform create remote-macosx
  Platform: remote-macosx
 Connected: no
(lldb) platform connect connect://localhost:1444
  Platform: remote-macosx
    Triple: x86_64-apple-darwin
OS Version: 10.6.7 (10J869)
    Kernel: Darwin Kernel Version 10.7.0: Sat Jan 29 15:17:16 PST 2011; root:xnu-1504.9.37~1/RELEASE_I386
  Hostname: machine1.foo.com
 Connected: yes
(lldb) platform process list 
PID    PARENT USER       GROUP      EFF USER   EFF GROUP  TRIPLE                   NAME
====== ====== ========== ========== ========== ========== ======================== ============================
99556  244    username   usergroup  username   usergroup  x86_64-apple-darwin      trustevaluation
99548  65539  username   usergroup  username   usergroup  x86_64-apple-darwin      lldb
99538  1      username   usergroup  username   usergroup  x86_64-apple-darwin      FileMerge
94943  1      username   usergroup  username   usergroup  x86_64-apple-darwin      mdworker
94852  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Safari

The lldb-platform implements everything with the Host:: layer, so this should
"just work" for linux. I will probably be adding more stuff to the Host layer
for launching processes and attaching to processes so that this support should
eventually just work as well.

Modified the target to be able to be created with an architecture that differs
from the main executable. This is needed for iOS debugging since we can have
an "armv6" binary which can run on an "armv7" machine, so we want to be able
to do:

% lldb
(lldb) platform create remote-ios
(lldb) file --arch armv7 a.out

Where "a.out" is an armv6 executable. The platform then can correctly decide
to open all "armv7" images for all dependent shared libraries.

Modified the disassembly to show the current PC value. Example output:

(lldb) disassemble --frame
a.out`main:
   0x1eb7:  pushl  %ebp
   0x1eb8:  movl   %esp, %ebp
   0x1eba:  pushl  %ebx
   0x1ebb:  subl   $20, %esp
   0x1ebe:  calll  0x1ec3                   ; main + 12 at test.c:18
   0x1ec3:  popl   %ebx
-> 0x1ec4:  calll  0x1f12                   ; getpid
   0x1ec9:  movl   %eax, 4(%esp)
   0x1ecd:  leal   199(%ebx), %eax
   0x1ed3:  movl   %eax, (%esp)
   0x1ed6:  calll  0x1f18                   ; printf
   0x1edb:  leal   213(%ebx), %eax
   0x1ee1:  movl   %eax, (%esp)
   0x1ee4:  calll  0x1f1e                   ; puts
   0x1ee9:  calll  0x1f0c                   ; getchar
   0x1eee:  movl   $20, (%esp)
   0x1ef5:  calll  0x1e6a                   ; sleep_loop at test.c:6
   0x1efa:  movl   $12, %eax
   0x1eff:  addl   $20, %esp
   0x1f02:  popl   %ebx
   0x1f03:  leave
   0x1f04:  ret
   
This can be handy when dealing with the new --line options that was recently
added:

(lldb) disassemble --line
a.out`main + 13 at test.c:19
   18  	{
-> 19  		printf("Process: %i\n\n", getpid());
   20  	    puts("Press any key to continue..."); getchar();
-> 0x1ec4:  calll  0x1f12                   ; getpid
   0x1ec9:  movl   %eax, 4(%esp)
   0x1ecd:  leal   199(%ebx), %eax
   0x1ed3:  movl   %eax, (%esp)
   0x1ed6:  calll  0x1f18                   ; printf

Modified the ModuleList to have a lookup based solely on a UUID. Since the
UUID is typically the MD5 checksum of a binary image, there is no need
to give the path and architecture when searching for a pre-existing
image in an image list.

Now that we support remote debugging a bit better, our lldb_private::Module
needs to be able to track what the original path for file was as the platform
knows it, as well as where the file is locally. The module has the two 
following functions to retrieve both paths:

const FileSpec &Module::GetFileSpec () const;
const FileSpec &Module::GetPlatformFileSpec () const;

llvm-svn: 128563
2011-03-30 18:16:51 +00:00
Caroline Tice 23443245e7 Fill in EmulateLDRDRegister to emulate LDRD (register) instruction.
Remove stubs for functions not-to-be-implemented at the moment.

llvm-svn: 128559
2011-03-30 17:54:52 +00:00
Caroline Tice f0901227e3 Fill in EmulateLDRLImmediate to emulate the LDRD (immediate) ARM instruction.
llvm-svn: 128556
2011-03-30 17:11:45 +00:00
Caroline Tice e746dbf83b Fix typo in previous check-in.
llvm-svn: 128549
2011-03-30 16:05:23 +00:00
Caroline Tice 527637d64a Fill in EmulateSTRImmARM to emulate the STR (immediate,ARM) instruction.
llvm-svn: 128528
2011-03-30 06:03:24 +00:00
Caroline Tice a0e8cd5e89 Fill in EmulateSTRBImmARM to emulate the STRB (immediate, ARM) instruction.
llvm-svn: 128527
2011-03-30 05:40:56 +00:00
Caroline Tice 4cee4bd9f4 Fill in EmulateSTREX to emulate the STREX ARM instruction.
llvm-svn: 128525
2011-03-30 05:15:46 +00:00
Caroline Tice 799e203894 Fill in code in EmulateSUBReg to emulate the SUB (register) ARM instruction.
llvm-svn: 128508
2011-03-29 23:44:20 +00:00
Caroline Tice c5bcda4619 Fill in code in EmulateADDRegShift, to emulate the ADD
(register-shifted register) ARM instruction.

llvm-svn: 128500
2011-03-29 23:03:16 +00:00
Caroline Tice eba8f83479 Add subtraction context.
Add code to emulate SUB (SP minus register) ARM instruction.

Add stubs for other ARM emulation functions that need to be written.

llvm-svn: 128491
2011-03-29 21:24:06 +00:00
Caroline Tice 3f0bfdacc1 Add missing encodings for EmulateMOVRdImm (MOV register) function.
llvm-svn: 128479
2011-03-29 19:53:44 +00:00
Caroline Tice 87c19f61d4 Fix single quote characters throughout the ARM emulation stuff.
Fix bugs in various ARM istruction emulation functions:

EmulateVPUSH
   - Fix context.
   - Fix bug calculating register numbers.

EmulateVPOP
   - Fix context.
   - Fix bug calculating register numbers.

EmulateShiftIMM
   - Fix bug in assert statement.

EmulateLDMDA
   - Fix context.

EmulateLDMDB
   - Fix context.

EmulateLDMIB
   - Fix context.     

EmulateSTM
   - Fix bug calculating lowest_set_bit.     

EmulateSTMDA
   - Fix context.
   - Fix bug calculating lowest_set_bit.

EmulateSTMDB
   - Fix context.
   - Fix bug calculating lowest_set_bit.

EmulateSTMIB
   - FIx context     

EmulateLDRSBImmed
   - Fix test to match correction in corrected manual 

llvm-svn: 128409
2011-03-28 16:10:45 +00:00
Greg Clayton 0ae962735f Made the lldb_private::Opcode struct into a real boy... I mean class.
Modified the Disassembler::Instruction base class to contain an Opcode 
instance so that we can know the bytes for an instruction without needing
to keep the data around.

Modified the DisassemblerLLVM's instruction class to correctly extract the
opcode bytes if all goes well.

llvm-svn: 128248
2011-03-24 23:53:38 +00:00
Greg Clayton e0d378b334 Fixed the LLDB build so that we can have private types, private enums and
public types and public enums. This was done to keep the SWIG stuff from
parsing all sorts of enums and types that weren't needed, and allows us to
abstract our API better.

llvm-svn: 128239
2011-03-24 21:19:54 +00:00
Caroline Tice 9b281e2214 Add missing encodings for EmulateLDRRtRnImm (ARM insn emulation funciton).
llvm-svn: 128229
2011-03-24 19:23:45 +00:00